Datasheet

Bits Name Description Type Reset
17 GPIO_QSPI_SD2_LEVEL_HIGH RO 0x0
16 GPIO_QSPI_SD2_LEVEL_LOW RO 0x0
15 GPIO_QSPI_SD1_EDGE_HIGH WC 0x0
14 GPIO_QSPI_SD1_EDGE_LOW WC 0x0
13 GPIO_QSPI_SD1_LEVEL_HIGH RO 0x0
12 GPIO_QSPI_SD1_LEVEL_LOW RO 0x0
11 GPIO_QSPI_SD0_EDGE_HIGH WC 0x0
10 GPIO_QSPI_SD0_EDGE_LOW WC 0x0
9 GPIO_QSPI_SD0_LEVEL_HIGH RO 0x0
8 GPIO_QSPI_SD0_LEVEL_LOW RO 0x0
7 GPIO_QSPI_SS_EDGE_HIGH WC 0x0
6 GPIO_QSPI_SS_EDGE_LOW WC 0x0
5 GPIO_QSPI_SS_LEVEL_HIGH RO 0x0
4 GPIO_QSPI_SS_LEVEL_LOW RO 0x0
3 GPIO_QSPI_SCLK_EDGE_HIGH WC 0x0
2 GPIO_QSPI_SCLK_EDGE_LOW WC 0x0
1 GPIO_QSPI_SCLK_LEVEL_HIGH RO 0x0
0 GPIO_QSPI_SCLK_LEVEL_LOW RO 0x0
IO_QSPI: PROC0_INTE Register
Offset: 0x34
Description
Interrupt Enable for proc0
Table 340.
PROC0_INTE Register
Bits Name Description Type Reset
31:24 Reserved. - - -
23 GPIO_QSPI_SD3_EDGE_HIGH RW 0x0
22 GPIO_QSPI_SD3_EDGE_LOW RW 0x0
21 GPIO_QSPI_SD3_LEVEL_HIGH RW 0x0
20 GPIO_QSPI_SD3_LEVEL_LOW RW 0x0
19 GPIO_QSPI_SD2_EDGE_HIGH RW 0x0
18 GPIO_QSPI_SD2_EDGE_LOW RW 0x0
17 GPIO_QSPI_SD2_LEVEL_HIGH RW 0x0
16 GPIO_QSPI_SD2_LEVEL_LOW RW 0x0
15 GPIO_QSPI_SD1_EDGE_HIGH RW 0x0
14 GPIO_QSPI_SD1_EDGE_LOW RW 0x0
13 GPIO_QSPI_SD1_LEVEL_HIGH RW 0x0
RP2040 Datasheet
2.19. GPIO 312