Datasheet

A status register, FIFO_ST, provides the following status signals:
•
Incoming FIFO contains data (VLD)
•
Outgoing FIFO has room for more data (RDY)
•
The incoming FIFO was read from while empty at some point in the past (ROE)
•
The outgoing FIFO was written to while full at some point in the past (WOF)
Writing to the outgoing FIFO while full, or reading from the incoming FIFO while empty, does not affect the FIFO state.
The current contents and level of the FIFO is preserved. However, this does represent some loss of data or reception of
invalid data by the software accessing the FIFO, so a sticky error flag is raised (ROE or WOF).
The SIO has a FIFO IRQ output for each core, mapped to system IRQ numbers 15 and 16. Each IRQ output is the logical
OR of the VLD, ROE and WOF bits in that core’s FIFO_ST register: that is, the IRQ is asserted if any of these three bits is high,
and clears again when they are all low. The ROE and WOF flags are cleared by writing any value to FIFO_ST, and the VLD flag
is cleared by reading data from the FIFO until empty.
If the corresponding interrupt line is enabled in the Cortex-M0+ NVIC, then the processor will take an interrupt each time
data appears in its FIFO, or if it has performed some invalid FIFO operation (read on empty, write on full). Typically Core
0 will use IRQ15 and core 1 will use IRQ16. If the IRQs are used the other way round then it is difficult for the core that
has been interrupted to correctly identify the reason for the interrupt as the core doesn’t have access to the other core’s
FIFO status register.

NOTE
ROE and WOF only become set if software misbehaves in some way. Generally, the interrupt handler will trigger when
data appears in the FIFO (raising the VLD flag), and the interrupt handler clears the IRQ by reading data from the FIFO
until VLD goes low once more.
The inter-processor FIFOs and the Cortex-M0+ Event signals are used by the bootrom (Section 2.8) wait_for_vector
routine, where core 1 remains in a sleep state until it is woken, and provided with its initial stack pointer, entry point and
vector table through the FIFO.
2.3.1.5. Integer Divider
The SIO provides one 8-cycle signed/unsigned divide/modulo module to each of the cores. Calculation is started by
writing a dividend and divisor to the two argument registers, DIVIDEND and DIVISOR. The divider calculates the quotient /
and remainder % of this division over the next 8 cycles, and on the 9th cycle the results can be read from the two result
registers DIV_QUOTIENT and DIV_REMAINDER. A 'ready' bit in register DIV_CSR can be polled to wait for the calculation
to complete, or software can insert a fixed 8-cycle delay.
SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_divider/divider.S Lines 10 - 30
10 .macro __divider_delay
11 // delay 8 cycles
12 b 1f
13 1: b 1f
14 1: b 1f
15 1: b 1f
16 1:
17 .endm
18
19 .align 2
20
21 regular_func_with_section hw_divider_divmod_s32
22 ldr r3, =(SIO_BASE)
23 str r0, [r3, #SIO_DIV_SDIVIDEND_OFFSET]
24 str r1, [r3, #SIO_DIV_SDIVISOR_OFFSET]
25 __divider_delay
RP2040 Datasheet
2.3. Processor subsystem 31