Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Bits Name Description Type Reset
6 GPIO_QSPI_SS_EDGE_LOW RO 0x0
5 GPIO_QSPI_SS_LEVEL_HIGH RO 0x0
4 GPIO_QSPI_SS_LEVEL_LOW RO 0x0
3 GPIO_QSPI_SCLK_EDGE_HIGH RO 0x0
2 GPIO_QSPI_SCLK_EDGE_LOW RO 0x0
1 GPIO_QSPI_SCLK_LEVEL_HIGH RO 0x0
0 GPIO_QSPI_SCLK_LEVEL_LOW RO 0x0
2.19.6.3. Pad Control - User Bank
The User Bank Pad Control registers start at a base address of 0x4001c000 (defined as PADS_BANK0_BASE in SDK).
Table 349. List of
PADS_BANK0
registers
Offset Name Info
0x00 VOLTAGE_SELECT Voltage select. Per bank control
0x04 GPIO0 Pad control register
0x08 GPIO1 Pad control register
0x0c GPIO2 Pad control register
0x10 GPIO3 Pad control register
0x14 GPIO4 Pad control register
0x18 GPIO5 Pad control register
0x1c GPIO6 Pad control register
0x20 GPIO7 Pad control register
0x24 GPIO8 Pad control register
0x28 GPIO9 Pad control register
0x2c GPIO10 Pad control register
0x30 GPIO11 Pad control register
0x34 GPIO12 Pad control register
0x38 GPIO13 Pad control register
0x3c GPIO14 Pad control register
0x40 GPIO15 Pad control register
0x44 GPIO16 Pad control register
0x48 GPIO17 Pad control register
0x4c GPIO18 Pad control register
0x50 GPIO19 Pad control register
0x54 GPIO20 Pad control register
0x58 GPIO21 Pad control register
0x5c GPIO22 Pad control register
RP2040 Datasheet
2.19. GPIO 320