Datasheet

◦
DAP Instance ID (to change the address that the SWD uses to communicate with the core in debug)
◦
Processor status (If the processor is halted, which may be useful in debug)
•
Processor IO config
◦
Input synchroniser control (to allow input synchronisers to be bypassed to reduce latency where clocks are
synchronous)
•
Debug control
◦
Provides the ability to control the SWD interface from inside the chip. This means Core 0 could debug Core 1,
which may make debug connectivity easier.
•
Memory power down (each memory can be powered down if not being used to save a small amount of extra
power).
2.21.2. List of Registers
The system config registers start at a base address of 0x40004000 (defined as SYSCFG_BASE in SDK).
Table 363. List of
SYSCFG registers
Offset Name Info
0x00 PROC0_NMI_MASK Processor core 0 NMI source mask
0x04 PROC1_NMI_MASK Processor core 1 NMI source mask
0x08 PROC_CONFIG Configuration for processors
0x0c PROC_IN_SYNC_BYPASS For each bit, if 1, bypass the input synchronizer between that
GPIO
and the GPIO input register in the SIO. The input synchronizers
should
generally be unbypassed, to avoid injecting metastabilities into
processors.
If you’re feeling brave, you can bypass to save two cycles of
input
latency. This register applies to GPIO 0…29.
0x10 PROC_IN_SYNC_BYPASS_HI For each bit, if 1, bypass the input synchronizer between that
GPIO
and the GPIO input register in the SIO. The input synchronizers
should
generally be unbypassed, to avoid injecting metastabilities into
processors.
If you’re feeling brave, you can bypass to save two cycles of
input
latency. This register applies to GPIO 30…35 (the QSPI IOs).
0x14 DBGFORCE Directly control the SWD debug port of either processor
0x18 MEMPOWERDOWN Control power downs to memories. Set high to power down
memories.
Use with extreme caution
SYSCFG: PROC0_NMI_MASK Register
Offset: 0x00
Description
Processor core 0 NMI source mask
RP2040 Datasheet
2.21. Syscfg 326