Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Table 364.
PROC0_NMI_MASK
Register
Bits Description Type Reset
31:0 Set a bit high to enable NMI from that IRQ RW 0x00000000
SYSCFG: PROC1_NMI_MASK Register
Offset: 0x04
Description
Processor core 1 NMI source mask
Table 365.
PROC1_NMI_MASK
Register
Bits Description Type Reset
31:0 Set a bit high to enable NMI from that IRQ RW 0x00000000
SYSCFG: PROC_CONFIG Register
Offset: 0x08
Description
Configuration for processors
Table 366.
PROC_CONFIG
Register
Bits Name Description Type Reset
31:28 PROC1_DAP_INST
ID
Configure proc1 DAP instance ID.
Recommend that this is NOT changed until you require
debug access in multi-chip environment
WARNING: do not set to 15 as this is reserved for
RescueDP
RW 0x1
27:24 PROC0_DAP_INST
ID
Configure proc0 DAP instance ID.
Recommend that this is NOT changed until you require
debug access in multi-chip environment
WARNING: do not set to 15 as this is reserved for
RescueDP
RW 0x0
23:2 Reserved. - - -
1 PROC1_HALTED Indication that proc1 has halted RO 0x0
0 PROC0_HALTED Indication that proc0 has halted RO 0x0
SYSCFG: PROC_IN_SYNC_BYPASS Register
Offset: 0x0c
Table 367.
PROC_IN_SYNC_BYPA
SS Register
Bits Description Type Reset
31:30 Reserved. - -
29:0 For each bit, if 1, bypass the input synchronizer between that GPIO
and the GPIO input register in the SIO. The input synchronizers should
generally be unbypassed, to avoid injecting metastabilities into processors.
If you’re feeling brave, you can bypass to save two cycles of input
latency. This register applies to GPIO 0…29.
RW 0x00000000
SYSCFG: PROC_IN_SYNC_BYPASS_HI Register
Offset: 0x10
RP2040 Datasheet
2.21. Syscfg 327