Datasheet

Table 368.
PROC_IN_SYNC_BYPA
SS_HI Register
Bits Description Type Reset
31:6 Reserved. - -
5:0 For each bit, if 1, bypass the input synchronizer between that GPIO
and the GPIO input register in the SIO. The input synchronizers should
generally be unbypassed, to avoid injecting metastabilities into processors.
If you’re feeling brave, you can bypass to save two cycles of input
latency. This register applies to GPIO 30…35 (the QSPI IOs).
RW 0x00
SYSCFG: DBGFORCE Register
Offset: 0x14
Description
Directly control the SWD debug port of either processor
Table 369. DBGFORCE
Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7 PROC1_ATTACH Attach processor 1 debug port to syscfg controls, and
disconnect it from external SWD pads.
RW 0x0
6 PROC1_SWCLK Directly drive processor 1 SWCLK, if PROC1_ATTACH is
set
RW 0x1
5 PROC1_SWDI Directly drive processor 1 SWDIO input, if PROC1_ATTACH
is set
RW 0x1
4 PROC1_SWDO Observe the value of processor 1 SWDIO output. RO -
3 PROC0_ATTACH Attach processor 0 debug port to syscfg controls, and
disconnect it from external SWD pads.
RW 0x0
2 PROC0_SWCLK Directly drive processor 0 SWCLK, if PROC0_ATTACH is
set
RW 0x1
1 PROC0_SWDI Directly drive processor 0 SWDIO input, if PROC0_ATTACH
is set
RW 0x1
0 PROC0_SWDO Observe the value of processor 0 SWDIO output. RO -
SYSCFG: MEMPOWERDOWN Register
Offset: 0x18
Description
Control power downs to memories. Set high to power down memories.
Use with extreme caution
Table 370.
MEMPOWERDOWN
Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7 ROM RW 0x0
6 USB RW 0x0
5 SRAM5 RW 0x0
4 SRAM4 RW 0x0
3 SRAM3 RW 0x0
RP2040 Datasheet
2.21. Syscfg 328