Datasheet

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3.2.3.2. Input Shift Register (ISR)
Figure 41. Input Shift
Register (ISR). Data
enters 1…32 bits at a
time, and current
contents is shifted left
or right to make room.
Once full, contents is
written to the RX FIFO.
•
IN instructions shift 1…32 bits at a time into the register.
•
PUSH instructions write the ISR contents to the RX FIFO.
•
The ISR is cleared to all-zeroes when pushed.
•
The state machine will automatically push the ISR on an IN instruction, once some shift threshold is reached, if
autopush is enabled.
•
Shift direction is configurable by the processor via configuration registers
Some peripherals, like UARTs, must shift in from the left to get correct bit order, since the wire order is LSB-first;
however, the processor may expect the resulting byte to be right-aligned. This is solved by the special null input source,
which allows the programmer to shift some number of zeroes into the ISR, following the data.
3.2.3.3. Shift Counters
State machines remember how many bits, in total, have been shifted out of the OSR via OUT instructions, and into the ISR
via IN instructions. This information is tracked at all times by a pair of hardware counters — the output shift counter and
the input shift counter — each capable of holding values from 0 to 32 inclusive. With each shift operation, the relevant
counter is incremented by the shift count, up to the maximum value of 32 (equal to the width of the shift register). The
state machine can be configured to perform certain actions when a counter reaches a configurable threshold:
•
The OSR can be automatically refilled once some number of bits have been shifted out. See Section 3.5.4
•
The ISR can be automatically emptied once some number of bits have been shifted in. See Section 3.5.4
•
PUSH or PULL instructions can be conditioned on the input or output shift counter, respectively
On PIO reset, or the assertion of CTRL_SM_RESTART, the input shift counter is cleared to 0 (nothing yet shifted in), and the
output shift counter is initialised to 32 (nothing remaining to be shifted out; fully exhausted). Some other instructions
affect the shift counters:
•
A successful PULL clears the output shift counter to 0
•
A successful PUSH clears the input shift counter to 0
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MOV OSR, … (i.e. any MOV instruction that writes OSR) clears the output shift counter to 0
•
MOV ISR, … (i.e. any MOV instruction that writes ISR) clears the input shift counter to 0
•
OUT ISR, count sets the input shift counter to count
3.2.3.4. Scratch Registers
Each state machine has two 32-bit internal scratch registers, called X and Y.
They are used as:
•
Source/destination for IN/OUT/SET/MOV
•
Source for branch conditions
RP2040 Datasheet
3.2. Programmer’s Model 335