Datasheet

For example, suppose we wanted to produce a long pulse for "1" data bits, and a short pulse for "0" data bits:
Ê1 .program ws2812_led
Ê2
Ê3 public entry_point:
Ê4 pull
Ê5 set x, 23 ; Loop over 24 bits
Ê6 bitloop:
Ê7 set pins, 1 ; Drive pin high
Ê8 out y, 1 [5] ; Shift 1 bit out, and write it to y
Ê9 jmp !y skip ; Skip the extra delay if the bit was 0
10 nop [5]
11 skip:
12 set pins, 0 [5]
13 jmp x-- bitloop ; Jump if x nonzero, and decrement x
14 jmp entry_point
Here X is used as a loop counter, and Y is used as a temporary variable for branching on single bits from the OSR. This
program can be used to drive a WS2812 LED interface, although more compact implementations are possible (as few
as 3 instructions).
MOV allows the use of the scratch registers to save/restore the shift registers if, for example, you would like to repeatedly
shift out the same sequence.

NOTE
A much more compact WS2812 example (4 instructions total) is shown in Section 3.6.2
3.2.3.5. FIFOs
Each state machine has a pair of 4-word deep FIFOs, one for data transfer from system to state machine (TX), and the
other for state machine to system (RX). The TX FIFO is written to by system busmasters, such as a processor or DMA
controller, and the RX FIFO is written to by the state machine. FIFOs decouple the timing of the PIO state machines and
the system bus, allowing state machines to go for longer periods without processor intervention.
FIFOs also generate data request (DREQ) signals, which allow a system DMA controller to pace its reads/writes based
on the presence of data in an RX FIFO, or space for new data in a TX FIFO. This allows a processor to set up a long
transaction, potentially involving many kilobytes of data, which will proceed with no further processor intervention.
Often, a state machine is only transferring data in one direction. In this case the SHIFTCTRL_FJOIN option can merge the
two FIFOs into a single 8-entry FIFO going in one direction only. This is useful for high-bandwidth interfaces such as DPI.
3.2.4. Stalling
State machines may momentarily pause execution for a number of reasons:
•
A WAIT instruction’s condition is not yet met
•
A blocking PULL when the TX FIFO is empty, or a blocking PUSH when the RX FIFO is full
•
An IRQ WAIT instruction which has set an IRQ flag, and is waiting for it to clear
•
An OUT instruction when autopull is enabled, OSR has reached its shift threshold, and the TX FIFO is empty
•
An IN instruction when autopush is enabled, ISR reaches its shift threshold, and the RX FIFO is full
In this case, the program counter does not advance, and the state machine will continue executing this instruction on
the next cycle. If the instruction specifies some number of delay cycles before the next instruction starts, these do not
begin until after the stall clears.
RP2040 Datasheet
3.2. Programmer’s Model 336