Datasheet

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NOTE
Side-set (Section 3.5.1) is not affected by stalls, and always takes place on the first cycle of the attached instruction.
3.2.5. Pin Mapping
PIO controls the output level and direction of up to 32 GPIOs, and can observe their input levels. On every system clock
cycle, each state machine may do none, one, or both of the following:
•
Change the level or direction of some GPIOs via an OUT or SET instruction, or read some GPIOs via an IN instruction
•
Change the level or direction of some GPIOs via a side-set operation
Each of these operations is on one of four contiguous ranges of GPIOs, with the base and count of each range
configured via each state machine’s PINCTRL register. There is a range for each of OUT, SET, IN and side-set operations.
Each range can cover any of the GPIOs accessible to a given PIO block (on RP2040 this is the 30 user GPIOs), and the
ranges can overlap.
For each individual GPIO output (level and direction separately), PIO considers all 8 writes that may have occurred on
that cycle, and applies the write from the highest-numbered state machine. If the same state machine performs a SET
/OUT and a side-set on the same GPIO simultaneously, the side-set is used. If no state machine writes to this GPIO
output, its value does not change from the previous cycle.
Generally each state machine’s outputs are mapped to a distinct group of GPIOs, implementing some peripheral
interface.
3.2.6. IRQ Flags
IRQ flags are state bits which can be set or cleared by state machines or the system. There are 8 in total: all 8 are visible
to all state machines, and the lower 4 can also be masked into one of PIO’s interrupt request lines, via the IRQ0_INTE and
IRQ1_INTE control registers.
They have two main uses:
•
Asserting system level interrupts from a state machine program, and optionally waiting for the interrupt to be
acknowledged
•
Synchronising execution between two state machines
State machines interact with the flags via the IRQ and WAIT instructions.
3.2.7. Interactions Between State Machines
The instruction memory is implemented as a 1-write 4-read register file, so all four state machines can read an
instruction on the same cycle, without stalling.
There are three ways to apply the multiple state machines:
•
Pointing multiple state machines at the same program
•
Pointing multiple state machines at different programs
•
Using multiple state machines to run different parts of the same interface, e.g. TX and RX side of a UART, or
clock/hsync and pixel data on a DPI display
State machines can not communicate data, but they can synchronise with one another by using the IRQ flags. There are
8 flags total (the lower four of which can be masked for use as system IRQs), and each state machine can set or clear
any flag using the IRQ instruction, and can wait for a flag to go high or low using the WAIT IRQ instruction. This allows
cycle-accurate synchronisation between state machines.
RP2040 Datasheet
3.2. Programmer’s Model 337