Datasheet

Table 376. PIO
instruction encoding
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JMP
0 0 0 Delay/side-set Condition Address
WAIT
0 0 1 Delay/side-set Pol Source Index
IN
0 1 0 Delay/side-set Source Bit count
OUT
0 1 1 Delay/side-set Destination Bit count
PUSH
1 0 0 Delay/side-set 0 IfF Blk 0 0 0 0 0
PULL
1 0 0 Delay/side-set 1 IfE Blk 0 0 0 0 0
MOV
1 0 1 Delay/side-set Destination Op Source
IRQ
1 1 0 Delay/side-set 0 Clr Wait Index
SET
1 1 1 Delay/side-set Destination Data
All PIO instructions execute in one clock cycle.
The function of the 5-bit Delay/side-set field depends on the state machine’s SIDESET_COUNT configuration:
•
Up to 5 LSBs (5 minus SIDESET_COUNT) encode a number of idle cycles inserted between this instruction and the next.
•
Up to 5 MSBs, set by SIDESET_COUNT, encode a side-set (Section 3.5.1), which can assert a constant onto some
GPIOs, concurrently with main instruction execution.
3.4.2. JMP
3.4.2.1. Encoding
Bit: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
JMP
0 0 0 Delay/side-set Condition Address
3.4.2.2. Operation
Set program counter to Address if Condition is true, otherwise no operation.
Delay cycles on a JMP always take effect, whether Condition is true or false, and they take place after Condition is
evaluated and the program counter is updated.
•
Condition:
◦
000: (no condition): Always
◦
001: !X: scratch X zero
◦
010: X--: scratch X non-zero, post-decrement
◦
011: !Y: scratch Y zero
◦
100: Y--: scratch Y non-zero, post-decrement
◦
101: X!=Y: scratch X not equal scratch Y
◦
110: PIN: branch on input pin
◦
111: !OSRE: output shift register not empty
•
Address: Instruction address to jump to. In the instruction encoding this is an absolute address within the PIO
instruction memory.
RP2040 Datasheet
3.4. Instruction Set 341