Datasheet


NOTE
By sheer coincidence, the interpolators are extremely well suited to SNES MODE7-style graphics routines. For
example, on each core, INTERP0 can provide a stream of tile lookups for some affine transform, and INTERP1 can
provide offsets into the tiles for the same transform.
2.3.1.6.1. Lane Operations
0
1
MaskAccumulator 0
Add to BASE1
(for PEEK0/POP0)
Add to BASE2
(forms part of
PEEK2/POP2)
Result 0
Result 1
Accumulator 1
Right Shift
Sign-extend
fromMask
0
1
1
0
1
0
Figure 9. Each lane of
each interpolator can
be configured to
perform mask, shift
and sign-extension on
one of the
accumulators. This is
fed into adders which
produces final results,
which may optionally
be fed back into the
accumulators with
each read. The
datapath can be
configured using a
handful of 32-bit
multiplexers. From left
to right, these are
controlled by the
following CTRL flags:
CROSS_RESULT,
CROSS_INPUT,
SIGNED, ADD_RAW.
Each lane performs these three operations, in sequence:
•
A right shift by CTRL_LANEx_SHIFT (0 to 31 bits)
•
A mask of bits from CTRL_LANEx_MASK_LSB to CTRL_LANEx_MASK_MSB inclusive (each ranging from bit 0 to bit 31)
•
A sign extension from the top of the mask, i.e. take bit CTRL_LANEx_MASK_MSB and OR it into all more-significant bits, if
CTRL_LANEx_SIGNED is set
For example, if:
•
ACCUM0 = 0xdeadbeef
•
CTRL_LANE0_SHIFT = 8
•
CTRL_LANE0_MASK_LSB = 4
•
CTRL_LANE0_MASK_MSB = 7
•
CTRL_SIGNED = 1
Then lane 0 would produce the following results at each stage:
•
Right shift by 8 to produce 0x00deadbe
•
Mask bits 7 to 4 to produce 0x00deadbe & 0x000000f0 = 0x000000b0
•
Sign-extend up from bit 7 to produce 0xffffffb0
In software:
Pico Examples: https://github.com/raspberrypi/pico-examples/tree/master/interp/hello_interp/hello_interp.c Lines 25 - 46
25 void moving_mask() {
26 interp_config cfg = interp_default_config();
27 interp0->accum[0] = 0x1234abcd;
28
29 puts("Masking:");
30 printf("ACCUM0 = %08x\n", interp0->accum[0]);
31 for (int i = 0; i < 8; ++i) {
32 // LSB, then MSB. These are inclusive, so 0,31 means "the entire 32 bit register"
33 interp_config_set_mask(&cfg, i * 4, i * 4 + 3);
34 interp_set_config(interp0, 0, &cfg);
35 // Reading from ACCUMx_ADD returns the raw lane shift and mask value, without BASEx
Ê added
36 printf("Nibble %d: %08x\n", i, interp0->add_raw[0]);
37 }
38
RP2040 Datasheet
2.3. Processor subsystem 34