Datasheet

31 static inline pio_sm_config squarewave_wrap_program_get_default_config(uint offset) {
32 pio_sm_config c = pio_get_default_sm_config();
33 sm_config_set_wrap(&c, offset + squarewave_wrap_wrap_target, offset +
Ê squarewave_wrap_wrap);
34 return c;
35 }
36 #endif
This is raw output from the PIO assembler, pioasm, which has created a default pio_sm_config object containing the WRAP
register values from the program listing. The control register fields could also be initialised directly.

NOTE
WRAP_BOTTOM and WRAP_TOP are absolute addresses in the PIO instruction memory. If a program is loaded at an offset,
the wrap addresses must be adjusted accordingly.
The squarewave_wrap example has delay cycles inserted, so that it behaves identically to the original squarewave program.
Thanks to program wrapping, these can now be removed, so that the output toggles twice as fast, while maintaining an
even balance of high and low periods.
Pico Examples: https://github.com/raspberrypi/pico-examples/tree/master/pio/squarewave/squarewave_fast.pio Lines 12 - 18
12 .program squarewave_fast
13 ; Like squarewave_wrap, but remove the delay cycles so we can run twice as fast.
14 set pindirs, 1 ; Set pin to output
15 .wrap_target
16 set pins, 1 ; Drive pin high
17 set pins, 0 ; Drive pin low
18 .wrap
3.5.3. FIFO Joining
By default, each state machine possesses a 4-entry FIFO in each direction: one for data transfer from system to state
machine (TX), the other for the reverse direction (RX). However, many applications do not require bidirectional data
transfer between the system and an individual state machine, but may benefit from deeper FIFOs: in particular, high-
bandwidth interfaces such as DPI. For these cases, SHIFTCTRL_FJOIN can merge the two 4-entry FIFOs into a single 8-entry
FIFO.
Figure 42. Joinable
dual FIFO. A pair of
four-entry FIFOs,
implemented with four
data registers, a 1:4
decoder and a 4:1
multiplexer. Additional
multiplexing allows
write data and read
data to cross between
the TX and RX lanes,
so that all 8 entries
are accessible from
both ports
Another example is a UART: because the TX/CTS and RX/RTS parts a of a UART are asynchronous, they are
RP2040 Datasheet
3.5. Functional Details 353