Datasheet

implemented on two separate state machines. It would be wasteful to leave half of each state machine’s FIFO
resources idle. The ability to join the two halves into just a TX FIFO for the TX/CTS state machine, or just an RX FIFO in
the case of the RX/RTS state machine, allows full utilisation. A UART equipped with an 8-deep FIFO can be left alone for
twice as long between interrupts as one with only a 4-deep FIFO.
When one FIFO is increased in size (from 4 to 8), the other FIFO on that state machine is reduced to zero. For example, if
joining to TX, the RX FIFO is unavailable, and any PUSH instruction will stall. The RX FIFO will appear both RXFULL and
RXEMPTY in the FSTAT register. The converse is true if joining to RX: the TX FIFO is unavailable, and the TXFULL and TXEMPTY
bits for this state machine will both be set in FSTAT.
8 FIFO entries is sufficient for 1 word per clock through the RP2040 system DMA, provided the DMA is not slowed by
contention with other masters.

CAUTION
Changing FJOIN discards any data present in the state machine’s FIFOs. If this data is irreplaceable, it must be
drained beforehand.
3.5.4. Autopush and Autopull
With each OUT instruction, the OSR gradually empties, as data is shifted out. Once empty, it must be refilled: for example,
a PULL transfers one word of data from the TX FIFO to the OSR. Similarly, the ISR must be emptied once full. One
approach to this is a loop which performs a PULL after an appropriate amount of data has been shifted:
Ê1 .program manual_pull
Ê2 .side_set 1 opt
Ê3
Ê4 .wrap_target
Ê5 set x, 2 ; X = bit count - 2
Ê6 pull side 1 [1] ; Stall here if no TX data
Ê7 bitloop:
Ê8 out pins, 1 side 0 [1] ; Shift out data bit and toggle clock low
Ê9 jmp x-- bitloop side 1 [1] ; Loop runs 3 times
10 out pins, 1 side 0 ; Shift out last bit before reloading X
11 .wrap
This program shifts out 4 bits from each FIFO word, with an accompanying bit clock, at a constant rate of 1 bit per 4
cycles. When the TX FIFO is empty, it stalls with the clock high (noting that side-set still takes place on cycles where the
instruction stalls). Figure 43 shows how a state machine would execute this program.
RP2040 Datasheet
3.5. Functional Details 354