Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
clock
0 0 0 0 3232 0
0 0 0 0 00
2 3 4 51
Current Instruction
Stall
TX FIFO Empty
TX FIFO Pop
OSR Count (0=full)
RX FIFO Push
ISR Count (0=empty)
RX FIFO Push
INOUT OUT IN OUT
IN OUT IN INOUT OUT
Figure 44. Execution
of auto_push_pull
program. The state
machine stalls on an
OUT until data has
travelled through the
TX FIFO into the OSR.
Subsequently, the OSR
is refilled
simultaneously with
each OUT operation
(due to bit count of
32), and IN data
bypasses the ISR and
goes straight to the RX
FIFO. The state
machine stalls again
when the FIFO has
drained, and the OSR
is once again empty.
To trigger automatic push or pull at the correct time, the state machine tracks the total shift count of the ISR and OSR,
using a pair of saturating 6-bit counters.
•
At reset, or upon CTRL_SM_RESTART assertion, ISR shift counter is set to 0 (nothing shifted in), and OSR to 32 (nothing
left to be shifted out)
•
An OUT instruction increases the OSR shift counter by Bit count
•
An IN instruction increases the ISR shift counter by Bit count
•
A PULL instruction or autopull clears the OSR counter to 0
•
A PUSH instruction or autopush clears the ISR counter to 0
•
A MOV OSR, x or MOV ISR, x clears the OSR or ISR shift counter to 0, respectively
•
A OUT ISR, n instruction sets the ISR shift counter to n
On any OUT or IN instruction, the state machine compares the shift counters to the values of SHIFTCTRL_PULL_THRESH and
SHIFTCTRL_PUSH_THRESH to decide whether action is required. Autopull and autopush are individually enabled by the
SHIFTCTRL_AUTOPULL and SHIFTCTRL_AUTOPUSH fields.
3.5.4.1. Autopush Details
Pseudocode for an 'IN' with autopush enabled:
Ê1 isr = shift_in(isr, input())
Ê2 isr count = saturate(isr count + in count)
Ê3
Ê4 if rx count >= threshold:
Ê5 if rx fifo is full:
Ê6 stall
Ê7 else:
Ê8 push(isr)
Ê9 isr = 0
10 isr count = 0
Note that the hardware performs the above steps in a single machine clock cycle (unless there is a stall).
Threshold is configurable from 1 to 32.
3.5.4.2. Autopull Details
On non-'OUT' cycles, the hardware performs the equivalent of the following pseudocode:
RP2040 Datasheet
3.5. Functional Details 357