Datasheet

that the state machine runs at some steady pace, potentially much slower than the system clock.
Implementing the clock dividers in this way allows interfacing between the state machines and the system to be
simpler, lower-latency, and with a smaller footprint. The state machine is completely idle on cycles where clock enable
is low, though the system can still access the state machine’s FIFOs and change its configuration.
The clock dividers are 16-bit integer, 8-bit fractional, with first-order delta-sigma for the fractional divider. The clock
divisor can vary between 1 and 65536, in increments of .
If the clock divisor is set to 1, the state machine runs on every cycle, i.e. full speed:
System Clock
CLKDIV_INT
CLKDIV_FRAC
Clock Enable
CTRL_SM_ENABLE
1
.0
Figure 45. State
machine operation
with a clock divisor of
1. Once the state
machine is enabled via
the CTRL register, its
clock enable is
asserted on every
cycle.
In general, an integer clock divisor of n will cause the state machine to run 1 cycle in every n, giving an effective clock
speed of .
System Clock
CLKDIV_INT
CLKDIV_FRAC
Clock Enable
CTRL_SM_ENABLE
2
.0
Figure 46. Integer
clock divisors yield a
periodic clock enable.
The clock divider
repeatedly counts
down from n, and
emits an enable pulse
when it reaches 1.
Fractional division will maintain a steady state division rate of , where n and f are the integer and fractional
fields of this state machine’s CLKDIV register. It does this by selectively extending some division periods from cycles to
.
System Clock
CLKDIV_INT
CLKDIV_FRAC
Clock Enable
CTRL_SM_ENABLE
2
.5
Figure 47. Fractional
clock division with an
average divisor of 2.5.
The clock divider
maintains a running
total of the fractional
value from each
division period, and
every time this value
wraps through 1, the
integer divisor is
increased by one for
the next division
period.
For small n, the jitter introduced by a fractional divider may be unacceptable. However, for larger values, this effect is
much less apparent.

NOTE
For fast asynchronous serial, it is recommended to use even divisions or multiples of 1 Mbaud where possible,
rather than the traditional multiples of 300, to avoid unnecessary jitter.
3.5.6. GPIO Mapping
Internally, PIO has a 32-bit register for the output levels of each GPIO it can drive, and another register for the output
enables (Hi/Lo-Z). On every system clock cycle, each state machine can write to some or all of the GPIOs in each of
these registers.
RP2040 Datasheet
3.5. Functional Details 359