Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
914
998
CTRL_LANE1_SIGNED controls whether BASE0 and BASE1 are sign-extended for this interpolation (this sign extension is
required because the interpolation produces an intermediate product value 40 bits in size). CTRL_LANE0_SIGNED continues
to control the sign extension of the lane 0 intermediate result in PEEK2, POP2 as normal.
Pico Examples: https://github.com/raspberrypi/pico-examples/tree/master/interp/hello_interp/hello_interp.c Lines 87 - 118
Ê87 void print_simple_blend2_results(bool is_signed) {
Ê88 // lane 1 signed flag controls whether base 0/1 are treated as signed or unsigned
Ê89 interp_config cfg = interp_default_config();
Ê90 interp_config_set_signed(&cfg, is_signed);
Ê91 interp_set_config(interp0, 1, &cfg);
Ê92
Ê93 for (int i = 0; i <= 6; i++) {
Ê94 interp0->accum[1] = 255 * i / 6;
Ê95 if (is_signed) {
Ê96 printf("%d\n", (int) interp0->peek[1]);
Ê97 } else {
Ê98 printf("0x%08x\n", (uint) interp0->peek[1]);
Ê99 }
100 }
101 }
102
103 void simple_blend2() {
104 puts("Simple blend 2:");
105
106 interp_config cfg = interp_default_config();
107 interp_config_set_blend(&cfg, true);
108 interp_set_config(interp0, 0, &cfg);
109
110 interp0->base[0] = -1000;
111 interp0->base[1] = 1000;
112
113 puts("signed:");
114 print_simple_blend2_results(true);
115
116 puts("unsigned:");
117 print_simple_blend2_results(false);
118 }
This should print:
signed:
-1000
-672
-336
-8
328
656
992
unsigned:
0xfffffc18
0xd5fffd60
0xaafffeb0
0x80fffff8
0x56000148
0x2c000290
RP2040 Datasheet
2.3. Processor subsystem 37