Datasheet

Figure 55. A 1-byte I2C
read transfer. In the
idle state, both lines
float high. The initiator
drives SDA low (a
Start condition),
followed by 7 address
bits A6-A0, and a
direction bit
(Read/nWrite). The
target drives SDA low
to acknowledge the
address (ACK). Data
bytes follow. The
target serialises data
on SDA, clocked out
by SCL. Every 9th
clock, the initiator
pulls SDA low to
acknowledge the data,
except on the last
byte, where it leaves
the line high (NAK).
Releasing SDA whilst
SCL is high is a Stop
condition, returning
the bus to idle.
I2C is an ubiquitous serial bus first described in the Dead Sea Scrolls, and later used by Philips Semiconductor. Two
wires with pullup resistors form an open-drain bus, and multiple agents address and signal one another over this bus by
driving the bus lines low, or releasing them to be pulled high. It has a number of unusual attributes:
•
SCL can be held low at any time, for any duration, by any member of the bus (not necessarily the target or initiator
of the transfer). This is known as clock stretching. The bus does not advance until all drivers release the clock.
•
Members of the bus can be a target of one transfer and initiate other transfers (the master/slave roles are not
fixed). However this is poorly supported by most I2C hardware.
•
SCL is not an edge-sensitive clock, rather SDA must be valid the entire time SCL is high
•
In spite of the transparency of SDA against SCL, transitions of SDA whilst SCL is high are used to mark beginning
and end of transfers (Start/Stop), or a new address phase within one (Restart)
The PIO program listed below handles serialisation, clock stretching, and checking of ACKs in the initiator role. It
provides a mechanism for escaping PIO instructions in the FIFO datastream, to issue Start/Stop/Restart sequences at
appropriate times. Provided no unexpected NAKs are received, this can perform long sequences of I2C transfers from a
DMA buffer, without processor intervention.
Pico Examples: https://github.com/raspberrypi/pico-examples/tree/master/pio/i2c/i2c.pio Lines 7 - 72
Ê7 .program i2c
Ê8 .side_set 1 opt pindirs
Ê9
10 ; TX Encoding:
11 ; | 15:10 | 9 | 8:1 | 0 |
12 ; | Instr | Final | Data | NAK |
13 ;
14 ; If Instr has a value n > 0, then this FIFO word has no
15 ; data payload, and the next n + 1 words will be executed as instructions.
16 ; Otherwise, shift out the 8 data bits, followed by the ACK bit.
17 ;
18 ; The Instr mechanism allows stop/start/repstart sequences to be programmed
19 ; by the processor, and then carried out by the state machine at defined points
20 ; in the datastream.
21 ;
22 ; The "Final" field should be set for the final byte in a transfer.
23 ; This tells the state machine to ignore a NAK: if this field is not
24 ; set, then any NAK will cause the state machine to halt and interrupt.
25 ;
26 ; Autopull should be enabled, with a threshold of 16.
27 ; Autopush should be enabled, with a threshold of 8.
28 ; The TX FIFO should be accessed with halfword writes, to ensure
29 ; the data is immediately available in the OSR.
30 ;
31 ; Pin mapping:
32 ; - Input pin 0 is SDA, 1 is SCL (if clock stretching used)
33 ; - Jump pin is SDA
34 ; - Side-set pin 0 is SCL
35 ; - Set pin 0 is SDA
36 ; - OUT pin 0 is SDA
37 ; - SCL must be SDA + 1 (for wait mapping)
38 ;
39 ; The OE outputs should be inverted in the system IO controls!
40 ; (It's possible for the inversion to be done in this program,
41 ; but costs 2 instructions: 1 for inversion, and one to cope
42 ; with the side effect of the MOV on TX shift counter.)
RP2040 Datasheet
3.6. Examples 380