Datasheet

Offset Name Info
0x028 RXF2 Direct read access to the RX FIFO for this state machine. Each
read pops one word from the FIFO. Attempting to read from an
empty FIFO has no effect on the FIFO state, and sets the sticky
FDEBUG_RXUNDER error flag for this FIFO. The data returned to
the system on a read from an empty FIFO is undefined.
0x02c RXF3 Direct read access to the RX FIFO for this state machine. Each
read pops one word from the FIFO. Attempting to read from an
empty FIFO has no effect on the FIFO state, and sets the sticky
FDEBUG_RXUNDER error flag for this FIFO. The data returned to
the system on a read from an empty FIFO is undefined.
0x030 IRQ State machine IRQ flags register. Write 1 to clear. There are 8
state machine IRQ flags, which can be set, cleared, and waited on
by the state machines. There’s no fixed association between
flags and state machines — any state machine can use any flag.
Any of the 8 flags can be used for timing synchronisation
between state machines, using IRQ and WAIT instructions. The
lower four of these flags are also routed out to system-level
interrupt requests, alongside FIFO status interrupts — see e.g.
IRQ0_INTE.
0x034 IRQ_FORCE Writing a 1 to each of these bits will forcibly assert the
corresponding IRQ. Note this is different to the INTF register:
writing here affects PIO internal state. INTF just asserts the
processor-facing IRQ signal for testing ISRs, and is not visible to
the state machines.
0x038 INPUT_SYNC_BYPASS There is a 2-flipflop synchronizer on each GPIO input, which
protects PIO logic from metastabilities. This increases input
delay, and for fast synchronous IO (e.g. SPI) these synchronizers
may need to be bypassed. Each bit in this register corresponds
to one GPIO.
0 → input is synchronized (default)
1 → synchronizer is bypassed
If in doubt, leave this register as all zeroes.
0x03c DBG_PADOUT Read to sample the pad output values PIO is currently driving to
the GPIOs. On RP2040 there are 30 GPIOs, so the two most
significant bits are hardwired to 0.
0x040 DBG_PADOE Read to sample the pad output enables (direction) PIO is
currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so
the two most significant bits are hardwired to 0.
0x044 DBG_CFGINFO The PIO hardware has some free parameters that may vary
between chip products.
These should be provided in the chip datasheet, but are also
exposed here.
0x048 INSTR_MEM0 Write-only access to instruction memory location 0
0x04c INSTR_MEM1 Write-only access to instruction memory location 1
0x050 INSTR_MEM2 Write-only access to instruction memory location 2
0x054 INSTR_MEM3 Write-only access to instruction memory location 3
0x058 INSTR_MEM4 Write-only access to instruction memory location 4
RP2040 Datasheet
3.7. List of Registers 388