Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Offset Name Info
0x0dc SM0_PINCTRL State machine pin control
0x0e0 SM1_CLKDIV Clock divisor register for state machine 1
Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
0x0e4 SM1_EXECCTRL Execution/behavioural settings for state machine 1
0x0e8 SM1_SHIFTCTRL Control behaviour of the input/output shift registers for state
machine 1
0x0ec SM1_ADDR Current instruction address of state machine 1
0x0f0 SM1_INSTR Read to see the instruction currently addressed by state machine
1’s program counter
Write to execute an instruction immediately (including jumps)
and then resume execution.
0x0f4 SM1_PINCTRL State machine pin control
0x0f8 SM2_CLKDIV Clock divisor register for state machine 2
Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
0x0fc SM2_EXECCTRL Execution/behavioural settings for state machine 2
0x100 SM2_SHIFTCTRL Control behaviour of the input/output shift registers for state
machine 2
0x104 SM2_ADDR Current instruction address of state machine 2
0x108 SM2_INSTR Read to see the instruction currently addressed by state machine
2’s program counter
Write to execute an instruction immediately (including jumps)
and then resume execution.
0x10c SM2_PINCTRL State machine pin control
0x110 SM3_CLKDIV Clock divisor register for state machine 3
Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
0x114 SM3_EXECCTRL Execution/behavioural settings for state machine 3
0x118 SM3_SHIFTCTRL Control behaviour of the input/output shift registers for state
machine 3
0x11c SM3_ADDR Current instruction address of state machine 3
0x120 SM3_INSTR Read to see the instruction currently addressed by state machine
3’s program counter
Write to execute an instruction immediately (including jumps)
and then resume execution.
0x124 SM3_PINCTRL State machine pin control
0x128 INTR Raw Interrupts
0x12c IRQ0_INTE Interrupt Enable for irq0
0x130 IRQ0_INTF Interrupt Force for irq0
0x134 IRQ0_INTS Interrupt status after masking & forcing for irq0
0x138 IRQ1_INTE Interrupt Enable for irq1
0x13c IRQ1_INTF Interrupt Force for irq1
0x140 IRQ1_INTS Interrupt status after masking & forcing for irq1
RP2040 Datasheet
3.7. List of Registers 390