Datasheet

Table 381. FLEVEL
Register
Bits Name Description Type Reset
31:28 RX3 RO 0x0
27:24 TX3 RO 0x0
23:20 RX2 RO 0x0
19:16 TX2 RO 0x0
15:12 RX1 RO 0x0
11:8 TX1 RO 0x0
7:4 RX0 RO 0x0
3:0 TX0 RO 0x0
PIO: TXF0, TXF1, TXF2, TXF3 Registers
Offsets: 0x010, 0x014, 0x018, 0x01c
Table 382. TXF0,
TXF1, TXF2, TXF3
Registers
Bits Description Type Reset
31:0 Direct write access to the TX FIFO for this state machine. Each write pushes
one word to the FIFO. Attempting to write to a full FIFO has no effect on the
FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this
FIFO.
WF 0x00000000
PIO: RXF0, RXF1, RXF2, RXF3 Registers
Offsets: 0x020, 0x024, 0x028, 0x02c
Table 383. RXF0,
RXF1, RXF2, RXF3
Registers
Bits Description Type Reset
31:0 Direct read access to the RX FIFO for this state machine. Each read pops one
word from the FIFO. Attempting to read from an empty FIFO has no effect on
the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO.
The data returned to the system on a read from an empty FIFO is undefined.
RF -
PIO: IRQ Register
Offset: 0x030
Table 384. IRQ
Register
Bits Description Type Reset
31:8 Reserved. - -
7:0 State machine IRQ flags register. Write 1 to clear. There are 8 state machine
IRQ flags, which can be set, cleared, and waited on by the state machines.
There’s no fixed association between flags and state machines — any state
machine can use any flag.
Any of the 8 flags can be used for timing synchronisation between state
machines, using IRQ and WAIT instructions. The lower four of these flags are
also routed out to system-level interrupt requests, alongside FIFO status
interrupts — see e.g. IRQ0_INTE.
WC 0x00
PIO: IRQ_FORCE Register
Offset: 0x034
RP2040 Datasheet
3.7. List of Registers 393