Datasheet

Table 385. IRQ_FORCE
Register
Bits Description Type Reset
31:8 Reserved. - -
7:0 Writing a 1 to each of these bits will forcibly assert the corresponding IRQ.
Note this is different to the INTF register: writing here affects PIO internal
state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is
not visible to the state machines.
WF 0x00
PIO: INPUT_SYNC_BYPASS Register
Offset: 0x038
Table 386.
INPUT_SYNC_BYPASS
Register
Bits Description Type Reset
31:0 There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic
from metastabilities. This increases input delay, and for fast synchronous IO
(e.g. SPI) these synchronizers may need to be bypassed. Each bit in this
register corresponds to one GPIO.
0 → input is synchronized (default)
1 → synchronizer is bypassed
If in doubt, leave this register as all zeroes.
RW 0x00000000
PIO: DBG_PADOUT Register
Offset: 0x03c
Table 387.
DBG_PADOUT Register
Bits Description Type Reset
31:0 Read to sample the pad output values PIO is currently driving to the GPIOs. On
RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to
0.
RO 0x00000000
PIO: DBG_PADOE Register
Offset: 0x040
Table 388.
DBG_PADOE Register
Bits Description Type Reset
31:0 Read to sample the pad output enables (direction) PIO is currently driving to
the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are
hardwired to 0.
RO 0x00000000
PIO: DBG_CFGINFO Register
Offset: 0x044
Description
The PIO hardware has some free parameters that may vary between chip products.
These should be provided in the chip datasheet, but are also exposed here.
Table 389.
DBG_CFGINFO
Register
Bits Name Description Type Reset
31:22 Reserved. - - -
21:16 IMEM_SIZE The size of the instruction memory, measured in units of
one instruction
RO -
15:12 Reserved. - - -
RP2040 Datasheet
3.7. List of Registers 394