Datasheet

Bits Name Description Type Reset
11:8 SM_COUNT The number of state machines this PIO instance is
equipped with.
RO -
7:6 Reserved. - - -
5:0 FIFO_DEPTH The depth of the state machine TX/RX FIFOs, measured in
words.
Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with
double
this depth.
RO -
PIO: INSTR_MEM0, INSTR_MEM1, …, INSTR_MEM30, INSTR_MEM31 Registers
Offsets: 0x048, 0x04c, …, 0x0c0, 0x0c4
Table 390.
INSTR_MEM0,
INSTR_MEM1, …,
INSTR_MEM30,
INSTR_MEM31
Registers
Bits Description Type Reset
31:16 Reserved. - -
15:0 Write-only access to instruction memory location N WO 0x0000
PIO: SM0_CLKDIV, SM1_CLKDIV, SM2_CLKDIV, SM3_CLKDIV Registers
Offsets: 0x0c8, 0x0e0, 0x0f8, 0x110
Description
Clock divisor register for state machine N
Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
Table 391.
SM0_CLKDIV,
SM1_CLKDIV,
SM2_CLKDIV,
SM3_CLKDIV
Registers
Bits Name Description Type Reset
31:16 INT Effective frequency is sysclk/(int + frac/256).
Value of 0 is interpreted as 65536. If INT is 0, FRAC must
also be 0.
RW 0x0001
15:8 FRAC Fractional part of clock divisor RW 0x00
7:0 Reserved. - - -
PIO: SM0_EXECCTRL, SM1_EXECCTRL, SM2_EXECCTRL, SM3_EXECCTRL
Registers
Offsets: 0x0cc, 0x0e4, 0x0fc, 0x114
Description
Execution/behavioural settings for state machine N
Table 392.
SM0_EXECCTRL,
SM1_EXECCTRL,
SM2_EXECCTRL,
SM3_EXECCTRL
Registers
Bits Name Description Type Reset
31 EXEC_STALLED If 1, an instruction written to SMx_INSTR is stalled, and
latched by the state machine. Will clear to 0 once this
instruction completes.
RO 0x0
30 SIDE_EN If 1, the MSB of the Delay/Side-set instruction field is used
as side-set enable, rather than a side-set data bit. This
allows instructions to perform side-set optionally, rather
than on every instruction, but the maximum possible side-
set width is reduced from 5 to 4. Note that the value of
PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
RW 0x0
RP2040 Datasheet
3.7. List of Registers 395