Datasheet

Bits Name Description Type Reset
24:20 PUSH_THRESH Number of bits shifted into ISR before autopush, or
conditional push (PUSH IFFULL), will take place.
Write 0 for value of 32.
RW 0x00
19 OUT_SHIFTDIR 1 = shift out of output shift register to right. 0 = to left. RW 0x1
18 IN_SHIFTDIR 1 = shift input shift register to right (data enters from left).
0 = to left.
RW 0x1
17 AUTOPULL Pull automatically when the output shift register is
emptied, i.e. on or following an OUT instruction which
causes the output shift counter to reach or exceed
PULL_THRESH.
RW 0x0
16 AUTOPUSH Push automatically when the input shift register is filled,
i.e. on an IN instruction which causes the input shift
counter to reach or exceed PUSH_THRESH.
RW 0x0
15:0 Reserved. - - -
PIO: SM0_ADDR, SM1_ADDR, SM2_ADDR, SM3_ADDR Registers
Offsets: 0x0d4, 0x0ec, 0x104, 0x11c
Table 394. SM0_ADDR,
SM1_ADDR,
SM2_ADDR,
SM3_ADDR Registers
Bits Description Type Reset
31:5 Reserved. - -
4:0 Current instruction address of state machine N RO 0x00
PIO: SM0_INSTR, SM1_INSTR, SM2_INSTR, SM3_INSTR Registers
Offsets: 0x0d8, 0x0f0, 0x108, 0x120
Table 395.
SM0_INSTR,
SM1_INSTR,
SM2_INSTR,
SM3_INSTR Registers
Bits Description Type Reset
31:16 Reserved. - -
15:0 Read to see the instruction currently addressed by state machine N's program
counter.
Write to execute an instruction immediately (including jumps) and then
resume execution.
RW -
PIO: SM0_PINCTRL, SM1_PINCTRL, SM2_PINCTRL, SM3_PINCTRL Registers
Offsets: 0x0dc, 0x0f4, 0x10c, 0x124
Description
State machine pin control
Table 396.
SM0_PINCTRL,
SM1_PINCTRL,
SM2_PINCTRL,
SM3_PINCTRL
Registers
Bits Name Description Type Reset
31:29 SIDESET_COUNT The number of MSBs of the Delay/Side-set instruction
field which are used for side-set. Inclusive of the enable
bit, if present. Minimum of 0 (all delay bits, no side-set)
and maximum of 5 (all side-set, no delay).
RW 0x0
28:26 SET_COUNT The number of pins asserted by a SET. In the range 0 to 5
inclusive.
RW 0x5
RP2040 Datasheet
3.7. List of Registers 397