Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Bits Name Description Type Reset
25:20 OUT_COUNT The number of pins asserted by an OUT PINS, OUT
PINDIRS or MOV PINS instruction. In the range 0 to 32
inclusive.
RW 0x00
19:15 IN_BASE The pin which is mapped to the least-significant bit of a
state machine’s IN data bus. Higher-numbered pins are
mapped to consecutively more-significant data bits, with a
modulo of 32 applied to pin number.
RW 0x00
14:10 SIDESET_BASE The lowest-numbered pin that will be affected by a side-
set operation. The MSBs of an instruction’s side-set/delay
field (up to 5, determined by SIDESET_COUNT) are used
for side-set data, with the remaining LSBs used for delay.
The least-significant bit of the side-set portion is the bit
written to this pin, with more-significant bits written to
higher-numbered pins.
RW 0x00
9:5 SET_BASE The lowest-numbered pin that will be affected by a SET
PINS or SET PINDIRS instruction. The data written to this
pin is the least-significant bit of the SET data.
RW 0x00
4:0 OUT_BASE The lowest-numbered pin that will be affected by an OUT
PINS, OUT PINDIRS or MOV PINS instruction. The data
written to this pin will always be the least-significant bit of
the OUT or MOV data.
RW 0x00
PIO: INTR Register
Offset: 0x128
Description
Raw Interrupts
Table 397. INTR
Register
Bits Name Description Type Reset
31:12 Reserved. - - -
11 SM3 RO 0x0
10 SM2 RO 0x0
9 SM1 RO 0x0
8 SM0 RO 0x0
7 SM3_TXNFULL RO 0x0
6 SM2_TXNFULL RO 0x0
5 SM1_TXNFULL RO 0x0
4 SM0_TXNFULL RO 0x0
3 SM3_RXNEMPTY RO 0x0
2 SM2_RXNEMPTY RO 0x0
1 SM1_RXNEMPTY RO 0x0
0 SM0_RXNEMPTY RO 0x0
PIO: IRQ0_INTE Register
RP2040 Datasheet
3.7. List of Registers 398