Datasheet

Table Of Contents
Bits Name Description Type Reset
25:20 OUT_COUNT The number of pins asserted by an OUT PINS, OUT
PINDIRS or MOV PINS instruction. In the range 0 to 32
inclusive.
RW 0x00
19:15 IN_BASE The pin which is mapped to the least-significant bit of a
state machine’s IN data bus. Higher-numbered pins are
mapped to consecutively more-significant data bits, with a
modulo of 32 applied to pin number.
RW 0x00
14:10 SIDESET_BASE The lowest-numbered pin that will be affected by a side-
set operation. The MSBs of an instruction’s side-set/delay
field (up to 5, determined by SIDESET_COUNT) are used
for side-set data, with the remaining LSBs used for delay.
The least-significant bit of the side-set portion is the bit
written to this pin, with more-significant bits written to
higher-numbered pins.
RW 0x00
9:5 SET_BASE The lowest-numbered pin that will be affected by a SET
PINS or SET PINDIRS instruction. The data written to this
pin is the least-significant bit of the SET data.
RW 0x00
4:0 OUT_BASE The lowest-numbered pin that will be affected by an OUT
PINS, OUT PINDIRS or MOV PINS instruction. The data
written to this pin will always be the least-significant bit of
the OUT or MOV data.
RW 0x00
PIO: INTR Register
Offset: 0x128
Description
Raw Interrupts
Table 397. INTR
Register
Bits Name Description Type Reset
31:12 Reserved. - - -
11 SM3 RO 0x0
10 SM2 RO 0x0
9 SM1 RO 0x0
8 SM0 RO 0x0
7 SM3_TXNFULL RO 0x0
6 SM2_TXNFULL RO 0x0
5 SM1_TXNFULL RO 0x0
4 SM0_TXNFULL RO 0x0
3 SM3_RXNEMPTY RO 0x0
2 SM2_RXNEMPTY RO 0x0
1 SM1_RXNEMPTY RO 0x0
0 SM0_RXNEMPTY RO 0x0
PIO: IRQ0_INTE Register
RP2040 Datasheet
3.7. List of Registers 398