Datasheet

Offset: 0x12c
Description
Interrupt Enable for irq0
Table 398. IRQ0_INTE
Register
Bits Name Description Type Reset
31:12 Reserved. - - -
11 SM3 RW 0x0
10 SM2 RW 0x0
9 SM1 RW 0x0
8 SM0 RW 0x0
7 SM3_TXNFULL RW 0x0
6 SM2_TXNFULL RW 0x0
5 SM1_TXNFULL RW 0x0
4 SM0_TXNFULL RW 0x0
3 SM3_RXNEMPTY RW 0x0
2 SM2_RXNEMPTY RW 0x0
1 SM1_RXNEMPTY RW 0x0
0 SM0_RXNEMPTY RW 0x0
PIO: IRQ0_INTF Register
Offset: 0x130
Description
Interrupt Force for irq0
Table 399. IRQ0_INTF
Register
Bits Name Description Type Reset
31:12 Reserved. - - -
11 SM3 RW 0x0
10 SM2 RW 0x0
9 SM1 RW 0x0
8 SM0 RW 0x0
7 SM3_TXNFULL RW 0x0
6 SM2_TXNFULL RW 0x0
5 SM1_TXNFULL RW 0x0
4 SM0_TXNFULL RW 0x0
3 SM3_RXNEMPTY RW 0x0
2 SM2_RXNEMPTY RW 0x0
1 SM1_RXNEMPTY RW 0x0
0 SM0_RXNEMPTY RW 0x0
PIO: IRQ0_INTS Register
RP2040 Datasheet
3.7. List of Registers 399