Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Chapter 4. Peripherals
4.1. USB
4.1.1. Overview
Prerequisite Knowledge Required
This section requires knowledge of the USB protocol. We recommend [usbmadesimple] if you are
unclear on the terminology used in this section (see References).
RP2040 contains a USB 2.0 controller that can operate as either:
•
a Full Speed device (12 Mbit/s)
•
a host that can communicate with both Low Speed (1.5 Mbit/s) and Full Speed devices. This includes multiple
downstream devices connected to a USB hub.
There is an integrated USB 1.1 PHY which interfaces the USB controller with the DP and DM pins of the chip.
4.1.1.1. Features
The USB controller hardware handles the low level USB protocol, meaning the main job of the programmer is to
configure the controller and then provide / consume data buffers in response to events on the bus. The controller
interrupts the processor when it needs attention. The USB controller has 4K of DPSRAM which is used for configuration
and data buffers.
4.1.1.1.1. Device Mode
•
USB 2.0 compatible Full Speed device (12 Mbps)
•
Supports up to 32 endpoints (Endpoints 0 → 15 in both in and out directions)
•
Supports Control, Isochronous, Bulk, and Interrupt endpoint types
•
Supports double buffering
•
3840 bytes of usable buffer space in DPSRAM. This is equivalent to 60 × 64-byte buffers.
4.1.1.1.2. Host Mode
•
Can communicate with Full Speed (12 Mbps) devices and Low Speed devices (1.5 Mbps)
•
Can communicate with multiple devices via a USB hub, including Low Speed devices connected to a Full Speed
hub
•
Can poll up to 15 interrupt endpoints in hardware. (Interrupt endpoints are used by hubs to notify the host of
connect/disconnect events, mice to notify the host of movement etc.)
RP2040 Datasheet
4.1. USB 402