Datasheet

4.1.2. Architecture
Figure 57. A simplified
overview of the USB
controller
architecture.
The USB controller is an area efficient design that muxes a device controller or host controller onto a common set of
components. Each component is detailed below.
4.1.2.1. USB PHY
The USB PHY provides the electrical interface between the USB DP and DM pins and the digital logic of the controller. The
DP and DM pins are a differential pair, meaning the values are always the inverse of each other, except to encode a
specific line state (SE0, etc). The USB PHY drives the DP and DM pins to transmit data, as well as performing a differential
receive of any incoming data. The USB PHY provides both single-ended and differential receive data to the line state
detection module.
The USB PHY has built in pull-up and pull-down resistors. If the controller is acting as a Full Speed device then the DP pin
is pulled up to indicate to the host that a Full Speed device has been connected. In host mode, a weak pull down is
applied to DP and DM so that the lines are pulled to a logical zero until the device pulls up DP for Full Speed or DM for Low
Speed.
4.1.2.2. Line state detection
The [usbspec] defines several line states (Bus Reset, Connected, Suspend, Resume, Data 1, Data 0, etc) that need to be
detected. The line state detection module has several state machines to detect these states and signal events to the
other hardware components. There is no shared clock signal in USB, so the RX data must be sampled by an internal
clock. The maximum data rate of USB Full Speed is 12 Mbps. The RX data is sampled at 48MHz, giving 4 clock cycles to
capture and filter the bus state. The line state detection module distributes the filtered RX data to the Serial RX Engine.
4.1.2.3. Serial RX Engine
The serial receive engine decodes receive data captured by the line state detection module. It produces the following
information:
•
The PID of the incoming data packet
•
The device address for the incoming data
•
The device endpoint for the incoming data
•
Data bytes
The serial receive engine also detects errors in RX data by performing a CRC check on the incoming data. Any errors are
signalled to the other hardware blocks and can raise an interrupt.
RP2040 Datasheet
4.1. USB 403