Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Offset Name Info
0x78 USB_PWR Overrides for the power signals in the event that the VBUS
signals are not hooked up to GPIO. Set the value of the override
and then the override enable to switch over to the override value.
0x7c USBPHY_DIRECT This register allows for direct control of the USB phy. Use in
conjunction with usbphy_direct_override register to enable each
override bit.
0x80 USBPHY_DIRECT_OVERRIDE Override enable for each control in usbphy_direct
0x84 USBPHY_TRIM Used to adjust trim values of USB phy pull down resistors.
0x8c INTR Raw Interrupts
0x90 INTE Interrupt Enable
0x94 INTF Interrupt Force
0x98 INTS Interrupt status after masking & forcing
USB: ADDR_ENDP Register
Offset: 0x00
Description
Device address and endpoint control
Table 408.
ADDR_ENDP Register
Bits Name Description Type Reset
31:20 Reserved. - - -
19:16 ENDPOINT Device endpoint to send data to. Only valid for HOST
mode.
RW 0x0
15:7 Reserved. - - -
6:0 ADDRESS In device mode, the address that the device should
respond to. Set in response to a SET_ADDR setup packet
from the host. In host mode set to the address of the
device to communicate with.
RW 0x00
USB: ADDR_ENDP1, ADDR_ENDP2, …, ADDR_ENDP14, ADDR_ENDP15
Registers
Offsets: 0x04, 0x08, …, 0x38, 0x3c
Description
Interrupt endpoint N. Only valid for HOST mode.
Table 409.
ADDR_ENDP1,
ADDR_ENDP2, …,
ADDR_ENDP14,
ADDR_ENDP15
Registers
Bits Name Description Type Reset
31:27 Reserved. - - -
26 INTEP_PREAMBL
E
Interrupt EP requires preamble (is a low speed device on a
full speed hub)
RW 0x0
25 INTEP_DIR Direction of the interrupt endpoint. In=0, Out=1 RW 0x0
24:20 Reserved. - - -
19:16 ENDPOINT Endpoint number of the interrupt endpoint RW 0x0
15:7 Reserved. - - -
RP2040 Datasheet
4.1. USB 418