Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Pico Examples: https://github.com/raspberrypi/pico-examples/tree/master/interp/hello_interp/hello_interp.c Lines 209 - 267
209 void texture_mapping_setup(uint8_t *texture, uint texture_width_bits, uint
Ê texture_height_bits,
210 uint uv_fractional_bits) {
211 interp_config cfg = interp_default_config();
212 // set add_raw flag to use raw (un-shifted and un-masked) lane accumulator value when
Ê adding
213 // it to the the lane base to make the lane result
214 interp_config_set_add_raw(&cfg, true);
215 interp_config_set_shift(&cfg, uv_fractional_bits);
216 interp_config_set_mask(&cfg, 0, texture_width_bits - 1);
217 interp_set_config(interp0, 0, &cfg);
218
219 interp_config_set_shift(&cfg, uv_fractional_bits - texture_width_bits);
220 interp_config_set_mask(&cfg, texture_width_bits, texture_width_bits +
Ê texture_height_bits - 1);
221 interp_set_config(interp0, 1, &cfg);
222
223 interp0->base[2] = (uintptr_t) texture;
224 }
225
226 void texture_mapped_span(uint8_t *output, uint32_t u, uint32_t v, uint32_t du, uint32_t dv,
Ê uint count) {
227 // u, v are texture coordinates in fixed point with uv_fractional_bits fractional bits
228 // du, dv are texture coordinate steps across the span in same fixed point.
229 interp0->accum[0] = u;
230 interp0->base[0] = du;
231 interp0->accum[1] = v;
232 interp0->base[1] = dv;
233 for (uint i = 0; i < count; i++) {
234 // equivalent to
235 // uint32_t sm_result0 = (accum0 >> uv_fractional_bits) & (1 << (texture_width_bits -
Ê 1);
236 // uint32_t sm_result1 = (accum1 >> uv_fractional_bits) & (1 << (texture_height_bits
Ê - 1);
237 // uint8_t *address = texture + sm_result0 + (sm_result1 << texture_width_bits);
238 // output[i] = *address;
239 // accum0 = du + accum0;
240 // accum1 = dv + accum1;
241
242 // result2 is the texture address for the current pixel;
243 // popping the result advances to the next iteration
244 output[i] = *(uint8_t *) interp0->pop[2];
245 }
246 }
247
248 void texture_mapping() {
249 puts("Affine Texture mapping (with texture wrap):");
250
251 uint8_t texture[] = {
252 0x00, 0x01, 0x02, 0x03,
253 0x10, 0x11, 0x12, 0x13,
254 0x20, 0x21, 0x22, 0x23,
255 0x30, 0x31, 0x32, 0x33,
256 };
257 // 4x4 texture
258 texture_mapping_setup(texture, 2, 2, 16);
259 uint8_t output[12];
260 uint32_t du = 65536 / 2; // step of 1/2
261 uint32_t dv = 65536 / 3; // step of 1/3
262 texture_mapped_span(output, 0, 0, du, dv, 12);
263
RP2040 Datasheet
2.3. Processor subsystem 41