Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Bits Name Description Type Reset
6:0 ADDRESS Device address RW 0x00
USB: MAIN_CTRL Register
Offset: 0x40
Description
Main control register
Table 410.
MAIN_CTRL Register
Bits Name Description Type Reset
31 SIM_TIMING Reduced timings for simulation RW 0x0
30:2 Reserved. - - -
1 HOST_NDEVICE Device mode = 0, Host mode = 1 RW 0x0
0 CONTROLLER_EN Enable controller RW 0x0
USB: SOF_WR Register
Offset: 0x44
Description
Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host
will increment the frame number by 1 each time.
Table 411. SOF_WR
Register
Bits Name Description Type Reset
31:11 Reserved. - - -
10:0 COUNT WF 0x000
USB: SOF_RD Register
Offset: 0x48
Description
Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host
mode the last SOF sent by the host.
Table 412. SOF_RD
Register
Bits Name Description Type Reset
31:11 Reserved. - - -
10:0 COUNT RO 0x000
USB: SIE_CTRL Register
Offset: 0x4c
Description
SIE control register
Table 413. SIE_CTRL
Register
Bits Name Description Type Reset
31 EP0_INT_STALL Device: Set bit in EP_STATUS_STALL_NAK when EP0
sends a STALL
RW 0x0
30 EP0_DOUBLE_BUF Device: EP0 single buffered = 0, double buffered = 1 RW 0x0
RP2040 Datasheet
4.1. USB 419