Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Bits Name Description Type Reset
29 EP0_INT_1BUF Device: Set bit in BUFF_STATUS for every buffer
completed on EP0
RW 0x0
28 EP0_INT_2BUF Device: Set bit in BUFF_STATUS for every 2 buffers
completed on EP0
RW 0x0
27 EP0_INT_NAK Device: Set bit in EP_STATUS_STALL_NAK when EP0
sends a NAK
RW 0x0
26 DIRECT_EN Direct bus drive enable RW 0x0
25 DIRECT_DP Direct control of DP RW 0x0
24 DIRECT_DM Direct control of DM RW 0x0
23:19 Reserved. - - -
18 TRANSCEIVER_PD Power down bus transceiver RW 0x0
17 RPU_OPT Device: Pull-up strength (0=1K2, 1=2k3) RW 0x0
16 PULLUP_EN Device: Enable pull up resistor RW 0x0
15 PULLDOWN_EN Host: Enable pull down resistors RW 0x0
14 Reserved. - - -
13 RESET_BUS Host: Reset bus SC 0x0
12 RESUME Device: Remote wakeup. Device can initiate its own
resume after suspend.
SC 0x0
11 VBUS_EN Host: Enable VBUS RW 0x0
10 KEEP_ALIVE_EN Host: Enable keep alive packet (for low speed bus) RW 0x0
9 SOF_EN Host: Enable SOF generation (for full speed bus) RW 0x0
8 SOF_SYNC Host: Delay packet(s) until after SOF RW 0x0
7 Reserved. - - -
6 PREAMBLE_EN Host: Preable enable for LS device on FS hub RW 0x0
5 Reserved. - - -
4 STOP_TRANS Host: Stop transaction SC 0x0
3 RECEIVE_DATA Host: Receive transaction (IN to host) RW 0x0
2 SEND_DATA Host: Send transaction (OUT from host) RW 0x0
1 SEND_SETUP Host: Send Setup packet RW 0x0
0 START_TRANS Host: Start transaction SC 0x0
USB: SIE_STATUS Register
Offset: 0x50
Description
SIE status register
Table 414.
SIE_STATUS Register
RP2040 Datasheet
4.1. USB 420