Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Bits Name Description Type Reset
22 EP11_IN RO 0x0
21 EP10_OUT RO 0x0
20 EP10_IN RO 0x0
19 EP9_OUT RO 0x0
18 EP9_IN RO 0x0
17 EP8_OUT RO 0x0
16 EP8_IN RO 0x0
15 EP7_OUT RO 0x0
14 EP7_IN RO 0x0
13 EP6_OUT RO 0x0
12 EP6_IN RO 0x0
11 EP5_OUT RO 0x0
10 EP5_IN RO 0x0
9 EP4_OUT RO 0x0
8 EP4_IN RO 0x0
7 EP3_OUT RO 0x0
6 EP3_IN RO 0x0
5 EP2_OUT RO 0x0
4 EP2_IN RO 0x0
3 EP1_OUT RO 0x0
2 EP1_IN RO 0x0
1 EP0_OUT RO 0x0
0 EP0_IN RO 0x0
USB: EP_ABORT Register
Offset: 0x60
Description
Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a
buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in
EP_ABORT_DONE is set when it is safe to modify the buffer control register.
Table 418. EP_ABORT
Register
Bits Name Description Type Reset
31 EP15_OUT RW 0x0
30 EP15_IN RW 0x0
29 EP14_OUT RW 0x0
28 EP14_IN RW 0x0
27 EP13_OUT RW 0x0
26 EP13_IN RW 0x0
RP2040 Datasheet
4.1. USB 424