Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Table 420.
EP_STALL_ARM
Register
Bits Name Description Type Reset
31:2 Reserved. - - -
1 EP0_OUT RW 0x0
0 EP0_IN RW 0x0
USB: NAK_POLL Register
Offset: 0x6c
Description
Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK.
Table 421. NAK_POLL
Register
Bits Name Description Type Reset
31:26 Reserved. - - -
25:16 DELAY_FS NAK polling interval for a full speed device RW 0x010
15:10 Reserved. - - -
9:0 DELAY_LS NAK polling interval for a low speed device RW 0x010
USB: EP_STATUS_STALL_NAK Register
Offset: 0x70
Description
Device: bits are set when the IRQ_ON_NAK or IRQ_ON_STALL bits are set. For EP0 this comes from SIE_CTRL. For all other
endpoints it comes from the endpoint control register.
Table 422.
EP_STATUS_STALL_N
AK Register
Bits Name Description Type Reset
31 EP15_OUT WC 0x0
30 EP15_IN WC 0x0
29 EP14_OUT WC 0x0
28 EP14_IN WC 0x0
27 EP13_OUT WC 0x0
26 EP13_IN WC 0x0
25 EP12_OUT WC 0x0
24 EP12_IN WC 0x0
23 EP11_OUT WC 0x0
22 EP11_IN WC 0x0
21 EP10_OUT WC 0x0
20 EP10_IN WC 0x0
19 EP9_OUT WC 0x0
18 EP9_IN WC 0x0
17 EP8_OUT WC 0x0
16 EP8_IN WC 0x0
15 EP7_OUT WC 0x0
RP2040 Datasheet
4.1. USB 427