Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
264 for (uint i = 0; i < 12; i++) {
265 printf("0x%02x\n", output[i]);
266 }
267 }
This should print:
0x00
0x00
0x01
0x01
0x12
0x12
0x13
0x23
0x20
0x20
0x31
0x31
2.3.1.7. List of Registers
The SIO registers start at a base address of 0xd0000000 (defined as SIO_BASE in SDK).
Table 16. List of SIO
registers
Offset Name Info
0x000 CPUID Processor core identifier
0x004 GPIO_IN Input value for GPIO pins
0x008 GPIO_HI_IN Input value for QSPI pins
0x010 GPIO_OUT GPIO output value
0x014 GPIO_OUT_SET GPIO output value set
0x018 GPIO_OUT_CLR GPIO output value clear
0x01c GPIO_OUT_XOR GPIO output value XOR
0x020 GPIO_OE GPIO output enable
0x024 GPIO_OE_SET GPIO output enable set
0x028 GPIO_OE_CLR GPIO output enable clear
0x02c GPIO_OE_XOR GPIO output enable XOR
0x030 GPIO_HI_OUT QSPI output value
0x034 GPIO_HI_OUT_SET QSPI output value set
0x038 GPIO_HI_OUT_CLR QSPI output value clear
0x03c GPIO_HI_OUT_XOR QSPI output value XOR
0x040 GPIO_HI_OE QSPI output enable
0x044 GPIO_HI_OE_SET QSPI output enable set
0x048 GPIO_HI_OE_CLR QSPI output enable clear
0x04c GPIO_HI_OE_XOR QSPI output enable XOR
RP2040 Datasheet
2.3. Processor subsystem 42