Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Bits Name Description Type Reset
2 VBUS_DETECT RW 0x0
1 VBUS_EN_OVERRIDE_EN RW 0x0
0 VBUS_EN RW 0x0
USB: USBPHY_DIRECT Register
Offset: 0x7c
Description
This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to
enable each override bit.
Table 425.
USBPHY_DIRECT
Register
Bits Name Description Type Reset
31:23 Reserved. - - -
22 DM_OVV DM over voltage RO 0x0
21 DP_OVV DP over voltage RO 0x0
20 DM_OVCN DM overcurrent RO 0x0
19 DP_OVCN DP overcurrent RO 0x0
18 RX_DM DPM pin state RO 0x0
17 RX_DP DPP pin state RO 0x0
16 RX_DD Differential RX RO 0x0
15 TX_DIFFMODE TX_DIFFMODE=0: Single ended mode
TX_DIFFMODE=1: Differential drive mode (TX_DM,
TX_DM_OE ignored)
RW 0x0
14 TX_FSSLEW TX_FSSLEW=0: Low speed slew rate
TX_FSSLEW=1: Full speed slew rate
RW 0x0
13 TX_PD TX power down override (if override enable is set). 1 =
powered down.
RW 0x0
12 RX_PD RX power down override (if override enable is set). 1 =
powered down.
RW 0x0
11 TX_DM Output data. TX_DIFFMODE=1, Ignored
TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to
enable drive. DPM=TX_DM
RW 0x0
10 TX_DP Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff
pair. TX_DP_OE=1 to enable drive. DPP=TX_DP,
DPM=~TX_DP
If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to
enable drive. DPP=TX_DP
RW 0x0
9 TX_DM_OE Output enable. If TX_DIFFMODE=1, Ignored.
If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z
state; 1 - DPM driving
RW 0x0
8 TX_DP_OE Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff
pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving
If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state;
1 - DPP driving
RW 0x0
RP2040 Datasheet
4.1. USB 429