Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Bits Name Description Type Reset
7 ERROR_RX_OVER
FLOW
Source: SIE_STATUS.RX_OVERFLOW RO 0x0
6 ERROR_RX_TIME
OUT
Source: SIE_STATUS.RX_TIMEOUT RO 0x0
5 ERROR_DATA_SE
Q
Source: SIE_STATUS.DATA_SEQ_ERROR RO 0x0
4 BUFF_STATUS Raised when any bit in BUFF_STATUS is set. Clear by
clearing all bits in BUFF_STATUS.
RO 0x0
3 TRANS_COMPLET
E
Raised every time SIE_STATUS.TRANS_COMPLETE is set.
Clear by writing to this bit.
RO 0x0
2 HOST_SOF Host: raised every time the host sends a SOF (Start of
Frame). Cleared by reading SOF_RD
RO 0x0
1 HOST_RESUME Host: raised when a device wakes up the host. Cleared by
writing to SIE_STATUS.RESUME
RO 0x0
0 HOST_CONN_DIS Host: raised when a device is connected or disconnected
(i.e. when SIE_STATUS.SPEED changes). Cleared by
writing to SIE_STATUS.SPEED
RO 0x0
References
▪
http://www.usbmadesimple.co.uk/
▪
https://www.usb.org/document-library/usb-20-specification
4.2. UART
ARM Documentation
Excerpted from the PrimeCell UART (PL011) Technical Reference Manual. Used with permission.
RP2040 has 2 identical instances of a UART peripheral, based on the ARM Primecell UART (PL011) (Revision r1p5).
Each instance supports the following features:
•
Separate 32x8 Tx and 32x12 Rx FIFOs
•
Programmable baud rate generator, clocked by clk_peri (see Section 2.15.1)
•
Standard asynchronous communication bits (start, stop, parity) added on transmit and removed on receive
•
line break detection
•
programmable serial interface (5, 6, 7, or 8 bits)
•
1 or 2 stop bits
•
programmable hardware flow control
Each UART can be connected to a number of GPIO pins as defined in the GPIO muxing table in Section 2.19.2.
Connections to the GPIO muxing are prefixed with the UART instance name uart0_ or uart1_, and include the following:
RP2040 Datasheet
4.2. UART 435