Datasheet

4.2.2.6. Transmit logic
The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. Control logic outputs
the serial bit stream beginning with a start bit, data bits with the Least Significant Bit (LSB) first, followed by the parity
bit, and then the stop bits according to the programmed configuration in control registers.
4.2.2.7. Receive logic
The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been
detected. Overrun, parity, frame error checking, and line break detection are also performed, and their status
accompanies the data that is written to the receive FIFO.
4.2.2.8. Interrupt generation logic
Individual maskable active HIGH interrupts are generated by the UART. A combined interrupt output is generated as an
OR function of the individual interrupt requests and is connected to the processor interrupt controllers.
See Section 4.2.6 for more information.
4.2.2.9. DMA interface
The UART provides an interface to connect to the DMA controller as UART DMA interface in Section 4.2.5 describes.
4.2.2.10. Synchronizing registers and logic
The UART supports both asynchronous and synchronous operation of the clocks, PCLK and UARTCLK. Synchronization
registers and handshaking logic have been implemented, and are active at all times. This has a minimal impact on
performance or area. Synchronization of control signals is performed on both directions of data flow, that is from the
PCLK to the UARTCLK domain, and from the UARTCLK to the PCLK domain.
4.2.3. Operation
4.2.3.1. Clock signals
The frequency selected for UARTCLK must accommodate the required range of baud rates:
•
FUARTCLK (min) ≥ 16 × baud_rate(max)
•
FUARTCLK(max) ≤ 16 × 65535 × baud_rate(min)
For example, for a range of baud rates from 110 baud to 460800 baud the UARTCLK frequency must be between
7.3728MHz to 115.34MHz.
The frequency of UARTCLK must also be within the required error limits for all baud rates to be used.
There is also a constraint on the ratio of clock frequencies for PCLK to UARTCLK. The frequency of UARTCLK must be
no more than 5/3 times faster than the frequency of PCLK:
•
FUARTCLK ≤ 5/3 × FPCLK
For example, in UART mode, to generate 921600 baud when UARTCLK is 14.7456MHz then PCLK must be greater than
or equal to 8.85276MHz. This ensures that the UART has sufficient time to write the received data to the receive FIFO.
RP2040 Datasheet
4.2. UART 438