Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Offset Name Info
0x050 FIFO_ST Status register for inter-core FIFOs (mailboxes).
0x054 FIFO_WR Write access to this core’s TX FIFO
0x058 FIFO_RD Read access to this core’s RX FIFO
0x05c SPINLOCK_ST Spinlock state
0x060 DIV_UDIVIDEND Divider unsigned dividend
0x064 DIV_UDIVISOR Divider unsigned divisor
0x068 DIV_SDIVIDEND Divider signed dividend
0x06c DIV_SDIVISOR Divider signed divisor
0x070 DIV_QUOTIENT Divider result quotient
0x074 DIV_REMAINDER Divider result remainder
0x078 DIV_CSR Control and status register for divider.
0x080 INTERP0_ACCUM0 Read/write access to accumulator 0
0x084 INTERP0_ACCUM1 Read/write access to accumulator 1
0x088 INTERP0_BASE0 Read/write access to BASE0 register.
0x08c INTERP0_BASE1 Read/write access to BASE1 register.
0x090 INTERP0_BASE2 Read/write access to BASE2 register.
0x094 INTERP0_POP_LANE0 Read LANE0 result, and simultaneously write lane results to both
accumulators (POP).
0x098 INTERP0_POP_LANE1 Read LANE1 result, and simultaneously write lane results to both
accumulators (POP).
0x09c INTERP0_POP_FULL Read FULL result, and simultaneously write lane results to both
accumulators (POP).
0x0a0 INTERP0_PEEK_LANE0 Read LANE0 result, without altering any internal state (PEEK).
0x0a4 INTERP0_PEEK_LANE1 Read LANE1 result, without altering any internal state (PEEK).
0x0a8 INTERP0_PEEK_FULL Read FULL result, without altering any internal state (PEEK).
0x0ac INTERP0_CTRL_LANE0 Control register for lane 0
0x0b0 INTERP0_CTRL_LANE1 Control register for lane 1
0x0b4 INTERP0_ACCUM0_ADD Values written here are atomically added to ACCUM0
0x0b8 INTERP0_ACCUM1_ADD Values written here are atomically added to ACCUM1
0x0bc INTERP0_BASE_1AND0 On write, the lower 16 bits go to BASE0, upper bits to BASE1
simultaneously.
0x0c0 INTERP1_ACCUM0 Read/write access to accumulator 0
0x0c4 INTERP1_ACCUM1 Read/write access to accumulator 1
0x0c8 INTERP1_BASE0 Read/write access to BASE0 register.
0x0cc INTERP1_BASE1 Read/write access to BASE1 register.
0x0d0 INTERP1_BASE2 Read/write access to BASE2 register.
RP2040 Datasheet
2.3. Processor subsystem 43