Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
57 uart_get_hw(uart)->cr = UART_UARTCR_UARTEN_BITS | UART_UARTCR_TXE_BITS |
Ê UART_UARTCR_RXE_BITS;
58 // Enable FIFOs
59 hw_set_bits(&uart_get_hw(uart)->lcr_h, UART_UARTLCR_H_FEN_BITS);
60 // Always enable DREQ signals -- no harm in this if DMA is not listening
61 uart_get_hw(uart)->dmacr = UART_UARTDMACR_TXDMAE_BITS | UART_UARTDMACR_RXDMAE_BITS;
62
63 return baud;
64 }
4.2.7.1. Baud Rate Calculation
The uart baud rate is derived from dividing clk_peri.
If the required baud rate is 115200 and UARTCLK = 125MHz then:
Baud Rate Divisor = (125 * 10^6)/(16 * 115200) ~= 67.817
Therefore, BRDI = 67 and BRDF = 0.817,
Therefore, fractional part, m = integer((0.817 * 64) + 0.5) = 52
Generated baud rate divider = 67 + 52/64 = 67.8125
Generated baud rate = (125 * 10^6)/(16 * 67.8125) ~= 115207
Error = (abs(115200 - 115207) / 115200) * 100 ~= 0.006%
SDK: https://github.com/raspberrypi/pico-sdk/tree/master/src/rp2_common/hardware_uart/uart.c Lines 73 - 99
73 uint uart_set_baudrate(uart_inst_t *uart, uint baudrate) {
74 invalid_params_if(UART, baudrate == 0);
75 uint32_t baud_rate_div = (8 * clock_get_hz(clk_peri) / baudrate);
76 uint32_t baud_ibrd = baud_rate_div >> 7;
77 uint32_t baud_fbrd;
78
79 if (baud_ibrd == 0) {
80 baud_ibrd = 1;
81 baud_fbrd = 0;
82 } else if (baud_ibrd >= 65535) {
83 baud_ibrd = 65535;
84 baud_fbrd = 0;
85 } else {
86 baud_fbrd = ((baud_rate_div & 0x7f) + 1) / 2;
87 }
88
89 // Load PL011's baud divisor registers
90 uart_get_hw(uart)->ibrd = baud_ibrd;
91 uart_get_hw(uart)->fbrd = baud_fbrd;
92
93 // PL011 needs a (dummy) line control register write to latch in the
94 // divisors. We don't want to actually change LCR contents here.
95 hw_set_bits(&uart_get_hw(uart)->lcr_h, 0);
96
97 // See datasheet
98 return (4 * clock_get_hz(clk_peri)) / (64 * baud_ibrd + baud_fbrd);
99 }
RP2040 Datasheet
4.2. UART 446