Datasheet

Bits Name Description Type Reset
10 BE Break error. This bit is set to 1 if a break condition was
detected, indicating that the received data input was held
LOW for longer than a full-word transmission time
(defined as start, data, parity and stop bits). In FIFO mode,
this error is associated with the character at the top of the
FIFO. When a break occurs, only one 0 character is loaded
into the FIFO. The next character is only enabled after the
receive data input goes to a 1 (marking state), and the
next valid start bit is received.
RO -
9 PE Parity error. When set to 1, it indicates that the parity of
the received data character does not match the parity that
the EPS and SPS bits in the Line Control Register,
UARTLCR_H. In FIFO mode, this error is associated with
the character at the top of the FIFO.
RO -
8 FE Framing error. When set to 1, it indicates that the received
character did not have a valid stop bit (a valid stop bit is
1). In FIFO mode, this error is associated with the
character at the top of the FIFO.
RO -
7:0 DATA Receive (read) data character. Transmit (write) data
character.
RWF -
UART: UARTRSR Register
Offset: 0x004
Description
Receive Status Register/Error Clear Register, UARTRSR/UARTECR
Table 437. UARTRSR
Register
Bits Name Description Type Reset
31:4 Reserved. - - -
3 OE Overrun error. This bit is set to 1 if data is received and the
FIFO is already full. This bit is cleared to 0 by a write to
UARTECR. The FIFO contents remain valid because no
more data is written when the FIFO is full, only the
contents of the shift register are overwritten. The CPU
must now read the data, to empty the FIFO.
WC 0x0
2 BE Break error. This bit is set to 1 if a break condition was
detected, indicating that the received data input was held
LOW for longer than a full-word transmission time
(defined as start, data, parity, and stop bits). This bit is
cleared to 0 after a write to UARTECR. In FIFO mode, this
error is associated with the character at the top of the
FIFO. When a break occurs, only one 0 character is loaded
into the FIFO. The next character is only enabled after the
receive data input goes to a 1 (marking state) and the next
valid start bit is received.
WC 0x0
RP2040 Datasheet
4.2. UART 448