Datasheet

Table 441. UARTFBRD
Register
Bits Name Description Type Reset
31:6 Reserved. - - -
5:0 BAUD_DIVFRAC The fractional baud rate divisor. These bits are cleared to
0 on reset.
RW 0x00
UART: UARTLCR_H Register
Offset: 0x02c
Description
Line Control Register, UARTLCR_H
Table 442.
UARTLCR_H Register
Bits Name Description Type Reset
31:8 Reserved. - - -
7 SPS Stick parity select. 0 = stick parity is disabled 1 = either: *
if the EPS bit is 0 then the parity bit is transmitted and
checked as a 1 * if the EPS bit is 1 then the parity bit is
transmitted and checked as a 0. This bit has no effect
when the PEN bit disables parity checking and generation.
RW 0x0
6:5 WLEN Word length. These bits indicate the number of data bits
transmitted or received in a frame as follows: b11 = 8 bits
b10 = 7 bits b01 = 6 bits b00 = 5 bits.
RW 0x0
4 FEN Enable FIFOs: 0 = FIFOs are disabled (character mode)
that is, the FIFOs become 1-byte-deep holding registers 1
= transmit and receive FIFO buffers are enabled (FIFO
mode).
RW 0x0
3 STP2 Two stop bits select. If this bit is set to 1, two stop bits are
transmitted at the end of the frame. The receive logic
does not check for two stop bits being received.
RW 0x0
2 EPS Even parity select. Controls the type of parity the UART
uses during transmission and reception: 0 = odd parity.
The UART generates or checks for an odd number of 1s in
the data and parity bits. 1 = even parity. The UART
generates or checks for an even number of 1s in the data
and parity bits. This bit has no effect when the PEN bit
disables parity checking and generation.
RW 0x0
1 PEN Parity enable: 0 = parity is disabled and no parity bit added
to the data frame 1 = parity checking and generation is
enabled.
RW 0x0
0 BRK Send break. If this bit is set to 1, a low-level is continually
output on the UARTTXD output, after completing
transmission of the current character. For the proper
execution of the break command, the software must set
this bit for at least two complete frames. For normal use,
this bit must be cleared to 0.
RW 0x0
UART: UARTCR Register
Offset: 0x030
RP2040 Datasheet
4.2. UART 451