Datasheet

Description
Control Register, UARTCR
Table 443. UARTCR
Register
Bits Name Description Type Reset
31:16 Reserved. - - -
15 CTSEN CTS hardware flow control enable. If this bit is set to 1,
CTS hardware flow control is enabled. Data is only
transmitted when the nUARTCTS signal is asserted.
RW 0x0
14 RTSEN RTS hardware flow control enable. If this bit is set to 1,
RTS hardware flow control is enabled. Data is only
requested when there is space in the receive FIFO for it to
be received.
RW 0x0
13 OUT2 This bit is the complement of the UART Out2 (nUARTOut2)
modem status output. That is, when the bit is
programmed to a 1, the output is 0. For DTE this can be
used as Ring Indicator (RI).
RW 0x0
12 OUT1 This bit is the complement of the UART Out1 (nUARTOut1)
modem status output. That is, when the bit is
programmed to a 1 the output is 0. For DTE this can be
used as Data Carrier Detect (DCD).
RW 0x0
11 RTS Request to send. This bit is the complement of the UART
request to send, nUARTRTS, modem status output. That
is, when the bit is programmed to a 1 then nUARTRTS is
LOW.
RW 0x0
10 DTR Data transmit ready. This bit is the complement of the
UART data transmit ready, nUARTDTR, modem status
output. That is, when the bit is programmed to a 1 then
nUARTDTR is LOW.
RW 0x0
9 RXE Receive enable. If this bit is set to 1, the receive section of
the UART is enabled. Data reception occurs for either
UART signals or SIR signals depending on the setting of
the SIREN bit. When the UART is disabled in the middle of
reception, it completes the current character before
stopping.
RW 0x1
8 TXE Transmit enable. If this bit is set to 1, the transmit section
of the UART is enabled. Data transmission occurs for
either UART signals, or SIR signals depending on the
setting of the SIREN bit. When the UART is disabled in the
middle of transmission, it completes the current character
before stopping.
RW 0x1
RP2040 Datasheet
4.2. UART 452