Datasheet

Bits Name Description Type Reset
5:3 RXIFLSEL Receive interrupt FIFO level select. The trigger points for
the receive interrupt are as follows: b000 = Receive FIFO
becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 /
4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 =
Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO
becomes >= 7 / 8 full b101-b111 = reserved.
RW 0x2
2:0 TXIFLSEL Transmit interrupt FIFO level select. The trigger points for
the transmit interrupt are as follows: b000 = Transmit
FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes
<= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full
b011 = Transmit FIFO becomes <= 3 / 4 full b100 =
Transmit FIFO becomes <= 7 / 8 full b101-b111 =
reserved.
RW 0x2
UART: UARTIMSC Register
Offset: 0x038
Description
Interrupt Mask Set/Clear Register, UARTIMSC
Table 445. UARTIMSC
Register
Bits Name Description Type Reset
31:11 Reserved. - - -
10 OEIM Overrun error interrupt mask. A read returns the current
mask for the UARTOEINTR interrupt. On a write of 1, the
mask of the UARTOEINTR interrupt is set. A write of 0
clears the mask.
RW 0x0
9 BEIM Break error interrupt mask. A read returns the current
mask for the UARTBEINTR interrupt. On a write of 1, the
mask of the UARTBEINTR interrupt is set. A write of 0
clears the mask.
RW 0x0
8 PEIM Parity error interrupt mask. A read returns the current
mask for the UARTPEINTR interrupt. On a write of 1, the
mask of the UARTPEINTR interrupt is set. A write of 0
clears the mask.
RW 0x0
7 FEIM Framing error interrupt mask. A read returns the current
mask for the UARTFEINTR interrupt. On a write of 1, the
mask of the UARTFEINTR interrupt is set. A write of 0
clears the mask.
RW 0x0
6 RTIM Receive timeout interrupt mask. A read returns the current
mask for the UARTRTINTR interrupt. On a write of 1, the
mask of the UARTRTINTR interrupt is set. A write of 0
clears the mask.
RW 0x0
5 TXIM Transmit interrupt mask. A read returns the current mask
for the UARTTXINTR interrupt. On a write of 1, the mask of
the UARTTXINTR interrupt is set. A write of 0 clears the
mask.
RW 0x0
RP2040 Datasheet
4.2. UART 454