Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
Offset Name Info
0x158 SPINLOCK22 Spinlock register 22
0x15c SPINLOCK23 Spinlock register 23
0x160 SPINLOCK24 Spinlock register 24
0x164 SPINLOCK25 Spinlock register 25
0x168 SPINLOCK26 Spinlock register 26
0x16c SPINLOCK27 Spinlock register 27
0x170 SPINLOCK28 Spinlock register 28
0x174 SPINLOCK29 Spinlock register 29
0x178 SPINLOCK30 Spinlock register 30
0x17c SPINLOCK31 Spinlock register 31
SIO: CPUID Register
Offset: 0x000
Description
Processor core identifier
Table 17. CPUID
Register
Bits Description Type Reset
31:0 Value is 0 when read from processor core 0, and 1 when read from processor
core 1.
RO -
SIO: GPIO_IN Register
Offset: 0x004
Description
Input value for GPIO pins
Table 18. GPIO_IN
Register
Bits Description Type Reset
31:30 Reserved. - -
29:0 Input value for GPIO0…29 RO 0x00000000
SIO: GPIO_HI_IN Register
Offset: 0x008
Description
Input value for QSPI pins
Table 19. GPIO_HI_IN
Register
Bits Description Type Reset
31:6 Reserved. - -
5:0 Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3 RO 0x00
SIO: GPIO_OUT Register
Offset: 0x010
RP2040 Datasheet
2.3. Processor subsystem 45