Datasheet

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RX FIFO/TX FIFO — Holds the RX FIFO and TX FIFO register banks and controllers, along with their status levels.
4.3.4. I2C Terminology
The following terms are used and are defined as follows:
4.3.4.1. I2C Bus Terms
The following terms relate to how the role of the I2C device and how it interacts with other I2C devices on the bus.
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Transmitter – the device that sends data to the bus. A transmitter can either be a device that initiates the data
transmission to the bus (a master-transmitter) or responds to a request from the master to send data to the bus (a
slave-transmitter).
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Receiver – the device that receives data from the bus. A receiver can either be a device that receives data on its
own request (a master-receiver) or in response to a request from the master (a slave-receiver).
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Master – the component that initializes a transfer (START command), generates the clock SCL signal and
terminates the transfer (STOP command). A master can be either a transmitter or a receiver.
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Slave – the device addressed by the master. A slave can be either receiver or transmitter.
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Multi-master – the ability for more than one master to co-exist on the bus at the same time without collision or
data loss.
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Arbitration – the predefined procedure that authorizes only one master at a time to take control of the bus. For
more information about this behaviour, refer to Section 4.3.8.
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Synchronization – the predefined procedure that synchronizes the clock signals provided by two or more masters.
For more information about this feature, refer to Section 4.3.9.
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SDA – data signal line (Serial Data)
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SCL – clock signal line (Serial Clock)
4.3.4.2. Bus Transfer Terms
The following terms are specific to data transfers that occur to/from the I2C bus.
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START (RESTART) – data transfer begins with a START or RESTART condition. The level of the SDA data line
changes from high to low, while the SCL clock line remains high. When this occurs, the bus becomes busy.

NOTE
START and RESTART conditions are functionally identical.
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STOP – data transfer is terminated by a STOP condition. This occurs when the level on the SDA data line passes
from the low state to the high state, while the SCL clock line remains high. When the data transfer has been
terminated, the bus is free or idle once again. The bus stays busy if a RESTART is generated instead of a STOP
condition.
4.3.5. I2C Behaviour
The DW_apb_i2c can be controlled via software to be either:
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An I2C master only, communicating with other I2C slaves; OR
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An I2C slave only, communicating with one or more I2C masters.
The master is responsible for generating the clock and controlling the transfer of data. The slave is responsible for
RP2040 Datasheet
4.3. I2C 463