Datasheet

SDA
SCL
1 2
S
Ack
(HIGH)
dummy
acknowledge
Sr
7 8 9
start byte 00000001
Figure 71. I2C Start
Byte Transfer
The START BYTE procedure is as follows:
1. Master generates a START condition.
2. Master transmits the START byte (0000 0001).
3. Master transmits the ACK clock pulse. (Present only to conform with the byte handling format used on the bus)
4. No slave sets the ACK signal to zero.
5. Master generates a RESTART (R) condition.
A hardware receiver does not respond to the START BYTE because it is a reserved address and resets after the
RESTART condition is generated.
4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
When operating as a master, the DW_apb_i2c component supports the mode of Tx FIFO management illustrated in
Figure 72
4.3.7.1. Tx FIFO Management
The component does not generate a STOP if the Tx FIFO becomes empty; in this situation the component holds the SCL
line low, stalling the bus until a new entry is available in the Tx FIFO. A STOP condition is generated only when the user
specifically requests it by setting bit nine (Stop bit) of the command written to IC_DATA_CMD register. Figure 72 shows
the bits in the IC_DATA_CMD register.
IC_DATA_CMD
Restart
Data Read/Write field; data retrieved from slave is read from
this field; data to be sent to slave is written to this field
CDM Write-only field; this bit determines whether transfer to
be carried out is Read (CMD=1) or Write (CMD=0)
Stop Write-only field; this bit determines whether STOP is
generated after data byte is sent or received
Restart Write-only field; this bit determines whether RESTART
(or STOP followed by START in case or restart
capability is not enabled) is generated before data is
sent or received
9 8 7 0
Stop CMD DATA
Figure 72.
IC_DATA_CMD
Register
Figure 73 illustrates the behaviour of the DW_apb_i2c when the Tx FIFO becomes empty while operating as a master
transmitter, as well as showing the generation of a STOP condition.
RP2040 Datasheet
4.3. I2C 468