Datasheet
Table Of Contents
- RP2040 Datasheet
- Colophon
- Chapter 1. Introduction
- Chapter 2. System Description
- 2.1. Bus Fabric
- 2.2. Address Map
- 2.3. Processor subsystem
- 2.4. Cortex-M0+
- 2.5. DMA
- 2.6. Memory
- 2.7. Boot Sequence
- 2.8. Bootrom
- 2.9. Power Supplies
- 2.10. Core Supply Regulator
- 2.11. Power Control
- 2.12. Chip-Level Reset
- 2.13. Power-On State Machine
- 2.14. Subsystem Resets
- 2.15. Clocks
- 2.16. Crystal Oscillator (XOSC)
- 2.17. Ring Oscillator (ROSC)
- 2.18. PLL
- 2.19. GPIO
- 2.20. Sysinfo
- 2.21. Syscfg
- 2.22. TBMAN
- Chapter 3. PIO
- Chapter 4. Peripherals
- 4.1. USB
- 4.2. UART
- 4.3. I2C
- 4.3.1. Features
- 4.3.2. IP Configuration
- 4.3.3. I2C Overview
- 4.3.4. I2C Terminology
- 4.3.5. I2C Behaviour
- 4.3.6. I2C Protocols
- 4.3.7. Tx FIFO Management and START, STOP and RESTART Generation
- 4.3.8. Multiple Master Arbitration
- 4.3.9. Clock Synchronization
- 4.3.10. Operation Modes
- 4.3.11. Spike Suppression
- 4.3.12. Fast Mode Plus Operation
- 4.3.13. Bus Clear Feature
- 4.3.14. IC_CLK Frequency Configuration
- 4.3.15. DMA Controller Interface
- 4.3.16. Operation of Interrupt Registers
- 4.3.17. List of Registers
- 4.4. SPI
- 4.5. PWM
- 4.6. Timer
- 4.7. Watchdog
- 4.8. RTC
- 4.9. ADC and Temperature Sensor
- 4.10. SSI
- 4.10.1. Overview
- 4.10.2. Features
- 4.10.3. IP Modifications
- 4.10.4. Clock Ratios
- 4.10.5. Transmit and Receive FIFO Buffers
- 4.10.6. 32-Bit Frame Size Support
- 4.10.7. SSI Interrupts
- 4.10.8. Transfer Modes
- 4.10.9. Operation Modes
- 4.10.10. Partner Connection Interfaces
- 4.10.11. DMA Controller Interface
- 4.10.12. APB Interface
- 4.10.13. List of Registers
- Chapter 5. Electrical and Mechanical
- Appendix A: Register Field Types
- Appendix B: Errata
- Appendix C: Documentation Release History
SDA
SCL
FIFO_
EMPTY
A
6
S
Tx FIFO loaded with data
(write data in this example)
Last byte popped from
Tx FIFO, with STOP bit
not set
Master releases SCL line and
resumes transmission because
new data became available
Data availability triggers
START condition on bus
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
A
3
A
2
A
1
A
0
D
6
D
7
D
5
D
4
D
3
D
2
D
1
D
0
W Ack Ack AckAck
P
Because STOP bit was not set on
last byte popped from Tx FIFO,
Master holds SCL low
Tx FIFO loaded
with new data
Last byte popped from Tx FIFO
with STOP bit set
STOP bit enabled triggers
STOP condition on bus
Figure 73. Master
Transmitter - Tx FIFO
Empties/STOP
Generation
Figure 74 illustrates the behaviour of the DW_apb_i2c when the Tx FIFO becomes empty while operating as a master
receiver, as well as showing the generation of a STOP condition.
SDA
SCL
FIFO_
EMPTY
A
6
S
Tx FIFO loaded with command
(read operation in this example)
Last command
popped from Tx
FIFO, with STOP bit
not set
Tx FIFO loaded
with new command
Last command popped from
Tx FIFO with STOP bit set
STOP bit enabled triggers
STOP condition on bus
Master releases SCL line and
resumes transmission
because new command
became available
Because STOP bit was
not set on last
command popped
from Tx FIFO, Master
holds SCL low
Command availability triggers
START condition on bus
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
R Ack Ack NakAck
S
Figure 74. Master
Receiver - Tx FIFO
Empties/STOP
Generation
Figure 75 and Figure 76 illustrate configurations where the user can control the generation of RESTART conditions on
the I2C bus. If bit 10 (Restart) of the IC_DATA_CMD register is set and the restart capability is enabled
(IC_RESTART_EN=1), a RESTART is generated before the data byte is written to or read from the slave. If the restart
capability is not enabled a STOP followed by a START is generated in place of the RESTART. Figure 75 illustrates this
situation during operation as a master transmitter.
SDA
SCL
FIFO_
EMPTY
A
6
S
Next byte in Tx FIFO
has RESTART bit set
Because next byte on Tx FIFO has
been tagged with RESTART bit,
Master issues RESTART and
initiates new transmission
Data availability triggers
START condition on bus
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
A
3
A
2
A
1
A
0
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
6
D
7
W Ack Ack AckWAck
S
R
Tx FIFO loaded with data
(write data in this example)
Figure 75. Master
Transmitter — Restart
Bit of IC_DATA_CMD
Is Set
Figure 76 illustrates the same situation, but during operation as a master receiver.
SDA
SCL
FIFO_
EMPTY
A
6
S
Tx FIFO loaded with command
(read operation in this example)
Next command in Tx FIFO
has RESTART bit set
Master issues NOT ACK as
required before RESTART
when operating as receiver
Because next command on Tx FIFO
has been tagged with RESTART bit,
Master issues RESTART and
initiates new transmission
Command availability triggers
START condition on bus
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
A
3
A
2
A
1
A
0
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
RR Ack Ack Nak Ack
S
R
Figure 76. Master
Receiver — Restart Bit
of IC_DATA_CMD Is
Set
Figure 77 illustrates operation as a master transmitter where the Stop bit of the IC_DATA_CMD register is set and the Tx
FIFO is not empty
SDA
SCL
FIFO_
EMPTY
A
6
S
Tx FIFO loaded with data
(write data in this example)
One byte (not last one)
is popped from Tx FIFO
with STOP bit set
Because more data is available in
Tx FIFO, a new transmission is
immediately initiated (provided
master is granted access to bus)
Data availability triggers
START condition on bus
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
A
3
A
2
A
1
A
0
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
6
D
7
W Ack Ack AckWAck
SP
Because STOP bit was set on last
byte popped from Tx FIFO, Master
generates STOP condition
Figure 77. Master
Transmitter — Stop Bit
of IC_DATA_CMD
Set/Tx FIFO Not Empty
Figure 78 illustrates operation as a master transmitter where the first byte loaded into the Tx FIFO is allowed to go
empty with the Restart bit set
RP2040 Datasheet
4.3. I2C 469