Datasheet

SDA
SCL
FIFO_
EMPTY
A
6
S
Last byte popped
from Tx FIFO with
STOP bit not set
Tx FIFO loaded
with new command
Master issues RESTART and
initiates new transmission
Because STOP bit was
not set on last byte
popped from Tx FIFO,
Master holds SCL low
Data availability triggers START
condition on bus
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
A
3
A
2
A
1
A
0
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
6
D
7
W Ack Ack AckWAck
S
R
Tx FIFO loaded with data
(write data in this example)
Figure 78. Master
Transmitter — First
Byte Loaded Into Tx
FIFO Allowed to
Empty, Restart Bit Set
Figure 79 illustrates operation as a master receiver where the Stop bit of the IC_DATA_CMD register is set and the Tx
FIFO is not empty
SDA
SCL
FIFO_
EMPTY
A
6
S
Tx FIFO loaded with command
(read operation in this example)
One command
(not last one) is
popped from
Tx FIFO with
STOP bit set
Because more commands
are available inTx FIFO, a
new transmission is
immediately initiated
(provided master is granted
access to bus)
Because STOP bit was
set on last command
popped from Tx FIFO,
Master generates
STOP condition
Command availability triggers
START condition on bus
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
A
3
A
2
A
1
A
0
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
RR Ack Ack Ack
SP
Nak
Figure 79. Master
Receiver — Stop Bit of
IC_DATA_CMD Set/Tx
FIFO Not Empty
Figure 80 illustrates operation as a master receiver where the first command loaded after the Tx FIFO is allowed to
empty and the Restart bit is set
SDA
SCL
FIFO_
EMPTY
A
6
S
Tx FIFO loaded with command
(read operation in this example)
Last command popped
from Tx FIFO with
STOP bit not set
Tx FIFO loaded
with new command
Next command loaded into
Tx FIFO has RESTART bit set
Master issues NOT ACK as
required before RESTART
when operating as receiver
Master issues RESTART and
initiates new transmission
Because STOP bit
was not set on last
command popped
from Tx FIFO, Master
holds SCL low
Command availability triggers
START condition on bus
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
A
5
A
4
A
3
A
2
A
1
A
0
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
7
D
6
RR Ack Ack Nak Ack
S
R
Figure 80. Master
Receiver — First
Command Loaded
After Tx FIFO Allowed
to Empty/Restart Bit
Set
4.3.8. Multiple Master Arbitration
The DW_apb_i2c bus protocol allows multiple masters to reside on the same bus. If there are two masters on the same
I2C-bus, there is an arbitration procedure if both try to take control of the bus at the same time by generating a START
condition at the same time. Once a master (for example, a microcontroller) has control of the bus, no other master can
take control until the first master sends a STOP condition and places the bus in an idle state.
Arbitration takes place on the SDA line, while the SCL line is one. The master, which transmits a one while the other master
transmits zero, loses arbitration and turns off its data output stage. The master that lost arbitration can continue to
generate clocks until the end of the byte transfer. If both masters are addressing the same slave device, the arbitration
could go into the data phase.
Upon detecting that it has lost arbitration to another master, the DW_apb_i2c will stop generating SCL (will disable the
output driver). Figure 81 illustrates the timing of when two masters are arbitrating on the bus.
RP2040 Datasheet
4.3. I2C 470