Datasheet

CLKA
DATA2
SDA
SCL
MSB
MSB
MSB
‘0’
matching data
DATA1 loses arbitration
SDA mirrors DATA2
SDA lines up
with DATA1
START condition
‘1’
Figure 81. Multiple
Master Arbitration
Control of the bus is determined by address or master code and data sent by competing masters, so there is no central
master nor any order of priority on the bus.
Arbitration is not allowed between the following conditions:
•
A RESTART condition and a data bit
•
A STOP condition and a data bit
•
A RESTART condition and a STOP condition

NOTE
Slaves are not involved in the arbitration process.
4.3.9. Clock Synchronization
When two or more masters try to transfer information on the bus at the same time, they must arbitrate and synchronize
the SCL clock. All masters generate their own clock to transfer messages. Data is valid only during the high period of SCL
clock. Clock synchronization is performed using the wired-AND connection to the SCL signal. When the master
transitions the SCL clock to zero, the master starts counting the low time of the SCL clock and transitions the SCL clock
signal to one at the beginning of the next clock period. However, if another master is holding the SCL line to 0, then the
master goes into a HIGH wait state until the SCL clock line transitions to one.
All masters then count off their high time, and the master with the shortest high time transitions the SCL line to zero. The
masters then count out their low time and the one with the longest low time forces the other masters into a HIGH wait
state. Therefore, a synchronized SCL clock is generated, which is illustrated in Figure 82. Optionally, slaves may hold the
SCL line low to slow down the timing on the I2C bus.
CLKA
CLKB
SCL
Wait State
SCL LOW transition Resets all CLKs
to start counting their LOW periods
SCL transitions HIGH when
all CLKs are in HIGH state
Start counting HIGH period
Figure 82. Multi-
Master Clock
Synchronization
RP2040 Datasheet
4.3. I2C 471