Datasheet


WARNING
It is recommended that the DW_apb_i2c Slave be brought out of reset only when the I2C bus is IDLE. De-asserting
the reset when a transfer is ongoing on the bus causes internal synchronization flip-flops used to synchronize SDA
and SCL to toggle from a reset value of one to the actual value on the bus. This can result in SDA toggling from one to
zero while SCL is one, thereby causing a false START condition to be detected by the DW_apb_i2c Slave. This
scenario can also be avoided by configuring the DW_apb_i2c with IC_SLAVE_DISABLE = 1 and IC_MASTER_MODE =
1 so that the Slave interface is disabled after reset. It can then be enabled by programming IC_CON[0] = 0 and
IC_CON[6] = 0 after the internal SDA and SCL have synchronized to the value on the bus; this takes approximately six
ic_clk cycles after reset de-assertion.
4.3.10.1.2. Slave-Transmitter Operation for a Single Byte
When another I2C master device on the bus addresses the DW_apb_i2c and requests data, the DW_apb_i2c acts as a
slave-transmitter and the following steps occur:
1. The other I2C master device initiates an I2C transfer with an address that matches the slave address in the IC_SAR
register of the DW_apb_i2c.
2. The DW_apb_i2c acknowledges the sent address and recognizes the direction of the transfer to indicate that it is
acting as a slave-transmitter.
3.
The DW_apb_i2c asserts the RD_REQ interrupt (bit five of the IC_RAW_INTR_STAT register) and holds the SCL line
low. It is in a wait state until software responds. If the RD_REQ interrupt has been masked, due to
IC_INTR_MASK.M_RD_REQ being set to zero, then it is recommended that a hardware and/or software timing
routine be used to instruct the CPU to perform periodic reads of the IC_RAW_INTR_STAT register.
a. Reads that indicate IC_RAW_INTR_STAT.R_RD_REQ being set to one must be treated as the equivalent of the
RD_REQ interrupt being asserted.
b. Software must then act to satisfy the I2C transfer.
c.
The timing interval used should be in the order of 10 times the fastest SCL clock period the DW_apb_i2c can
handle. For example, for 400 kb/s, the timing interval is 25μs.

NOTE
The value of 10 is recommended here because this is approximately the amount of time required for a single byte of
data transferred on the I2C bus.
1. If there is any data remaining in the Tx FIFO before receiving the read request, then the DW_apb_i2c asserts a
TX_ABRT interrupt (bit six of the IC_RAW_INTR_STAT register) to flush the old data from the TX FIFO. If the
TX_ABRT interrupt has been masked, due to IC_INTR_MASK.M_TX_ABRT being set to zero, then it is recommended
that re-using the timing routine (described in the previous step), or a similar one, be used to read the
IC_RAW_INTR_STAT register.

NOTE
Because the DW_apb_i2c’s Tx FIFO is forced into a flushed/reset state whenever a TX_ABRT event occurs, it is
necessary for software to release the DW_apb_i2c from this state by reading the IC_CLR_TX_ABRT register before
attempting to write into the Tx FIFO. See register IC_RAW_INTR_STAT for more details.
a. Reads that indicate bit six (R_TX_ABRT) being set to one must be treated as the equivalent of the TX_ABRT
interrupt being asserted.
b. There is no further action required from software.
c. The timing interval used should be similar to that described in the previous step for the
IC_RAW_INTR_STATRD_REQ register.
RP2040 Datasheet
4.3. I2C 473